CPU Physical Design Engineer

Job Title

CPU Physical Design Engineer

Role Summary

Responsible for physical implementation and signoff of custom CPU designs from RTL to GDS, delivering manufacturable core IP for client, server, IoT and AI processors. Works on physical design flow, verification, and optimization while collaborating with logic, circuit, architecture, full-chip design teams, and EDA vendors.

Experience Level

Mid-level. Typical experience expectations: Bachelor's degree plus ~6+ years relevant experience or Master's degree plus ~4+ years; demonstrated multi-year CPU physical design and tape-out experience preferred.

Responsibilities

Accountable for physical design implementation, verification, and performance optimization of CPU blocks and full-chip integration.

• Implement CPU blocks from RTL to GDS (synthesis, place-and-route, clock tree synthesis, floorplanning).
• Perform static timing analysis, timing closure, power/clock distribution and power/noise analysis.
• Execute verification and signoff flows: formal equivalence, STA signoff, reliability verification, power integrity and layout verification (DRC/LVS, ERC).
• Analyze results, recommend microarchitecture and physical changes to meet power, frequency, and area targets.
• Collaborate with logic, circuit, architecture, design-for-test, clocking and full-chip teams to balance timing, power and partitioning.
• Work with EDA vendors to enhance tool capabilities and automate physical design flows.
• Contribute to methodology and flow automation improvements.

Requirements

Must-have technical skills and proven chip-level delivery experience.

• Proven synthesis experience for digital logic blocks or partitions (multi-year experience in production flows).
• At least one completed tape-out on advanced process technologies.
• Experience with IC implementation tools and flows (examples: Synopsys/Cadence) including logic synthesis, place-and-route and design closure.
• PV convergence experience, including static timing and power analysis.
• Physical design verification experience: formal equivalence, electrical rule checking, DRC/LVS and noise flows.
• Scripting experience (TCL) for flow automation and tool integration.
• Ability to analyze signoff results and drive cross-functional fixes.

Nice-to-have:

• Extensive tape-out experience (multiple tape-outs) and deep knowledge of floor-planning, routing techniques and clock distribution for CPU designs.
• Strong expertise in STA, noise and reliability verification, RTL-to-GDS methodologies and formal equivalence at CPU level.
• Experience generating/verifying timing constraints and addressing timing violations at chip or block level.

Education Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering or a related field (commonly paired with ~6+ years relevant experience) or a Master’s degree (commonly paired with ~4+ years). Higher degrees acceptable. The posting also indicates requirements can be met through a combination of industry experience, internships, coursework or research (equivalent practical experience).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.