CPU PDN & EM/IR Sign-Off Engineer (Lead/Staff)

Job Title

CPU PDN & EM/IR Sign-Off Engineer (Lead/Staff)

Role Summary

Lead sign-off engineer responsible for power-delivery network (PDN) and electromagnetic/IR verification for CPU and high-performance cores at block and SoC levels. Works with SoC, packaging, CAD and EDA vendors to define PDN specs, validate IR/EM margins, and improve PDN implementation and automation.

Experience Level

Senior (Lead/Staff). The posting indicates 4–10 years of relevant experience; specific minimums vary by degree level.

Responsibilities

Key responsibilities include signoff, validation, planning, and collaboration across teams:

• Perform IR signoff for CPU/high-performance cores and run signal EM & power EM signoff at block and chip (top) level.
• Develop PG (power grid) specifications for hardware modules and validate PG grids using grid resistance and secondary PG resistance checks.
• Validate IR drops using static IR, dynamic IR (Vless) and VCD checks across die and package components.
• Plan IO, bump placement and RDL routing strategies; work on bump assignments and RDL enablement with packaging teams.
• Collaborate with SoC, packaging, and CAD teams to optimize package routing and overall PDN design.
• Partner with EDA vendors and internal CAD to develop and enhance automation flows and methodologies.
• Optimize compute/LSF usage for signoff runs and throughput.

Requirements

Must-have technical skills and experience:

• Hands-on PDN signoff experience using Redhawk, Redhawk_SC, and/or Voltus at block and SoC level.
• Strong understanding of power integrity and EM/IR signoff checks and methodologies.
• Proficient in scripting (Tcl, Perl) and experience with Python for automation.
• Familiarity with Innovus (or Fusion Compiler) for RDL, bump planning and PG ecosystem tasks.
• Experience with IO planning, bump planning, and RDL routing strategies.
• Ability to communicate effectively with global cross-functional teams and EDA vendors.
• Experience with compute cluster/LSF optimization for large signoff runs.

Nice-to-have:

• Hands-on power planning/floorplanning and physical verification experience.
• Experience with package routing optimizations and deeper PD (power distribution) expertise.

Education Requirements

Degree required: Bachelor's in Computer Science, Electrical/Electronics Engineering, or related engineering field with 4+ years of hardware engineering experience; OR Master's in a related field with 3+ years; OR PhD in a related field with 2+ years. The posting also lists "Bachelors - Electronics Engineering" specifically and indicates overall relevant experience of 4–10 years.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.