Job Title
CPU ML Microarchitect/RTL Engineer
Role Summary
Design and implement CPU machine-learning accelerator microarchitecture and RTL within Apple's Silicon Engineering Group (SEG). The role spans high-level architectural exploration through RTL development, verification support, and performance correlation to meet power, performance, area, and timing goals.
Experience Level
Mid-level β minimum 3+ years of relevant industry experience.
Responsibilities
The engineer will be responsible for:
- Micro-architecture development and specification from high-level exploration to detailed micro-architectural designs.
- RTL ownership: implement, assess, and refine RTL to meet power, performance, area, and timing objectives.
- Support verification efforts including test-bench development, formal methods, and simulation/emulation.
- Explore performance strategies and correlate microarchitectural decisions with performance verification results.
- Collaborate with cross-functional teams to deliver designs that meet timing, area, reliability, testability, and power targets.
Requirements
Must-have technical skills and experience:
- Experience with microprocessor architecture and RTL-driven microarchitectural design.
- Strong understanding of logic design principles with attention to timing and power implications.
- Proficiency in Verilog or VHDL for RTL development.
- Experience with simulators and waveform debugging processes.
- Track record working with verification teams and performance verification/correlation.
Education Requirements
Minimum Bachelor's degree (BS). The posting specifies "Minimum BS and 3+ years of relevant industry experience." No specific field of study or certifications were listed.
About the Company
Company: Apple
Headquarters: Cupertino, California, United States
Apple is a multinational technology company that designs, manufactures, and sells consumer electronics, software, and online services. Known for its innovative products such as the iPhone, Mac computers, and iPad, Apple emphasizes a strong commitment to high-quality design and user experience.

Date Posted: 2026-08-01