CPU Microarchitect, Vector and Matrix Compute

Job Title

CPU Microarchitect, Vector and Matrix Compute

Role Summary

Design and define the architecture and microarchitecture for high-performance RISC-V CPU vector (RVV), floating-point, and matrix compute execution units and subsystems to accelerate HPC and AI workloads. Work across hardware and software boundaries with architects, compiler/software teams, silicon designers, and external IP partners to translate workload requirements into scalable CPU designs that optimize performance, power, and area.

This is a remote role based in North America or Spain. The team values rigorous, cross-disciplinary engineering focused on measurable system-level results.

Experience Level

Mid-level — typical candidates have 5+ years of relevant CPU design and microarchitecture experience. The company may consider a range of seniorities during evaluation.

Responsibilities

Core responsibilities include driving architecture and microarchitecture for compute units and ensuring efficient execution of modern HPC and AI workloads.

• Lead architecture and micro-architecture for RISC-V CPU Vector (RVV), floating-point, and matrix compute execution units.
• Translate HPC/AI workload requirements into scalable CPU architectures that optimize performance, power, and area (PPA).
• Define execution pipelines, data paths, memory interfaces, cache-coherency interactions, and data-movement strategies.
• Collaborate with compiler/software teams, system architects, silicon designers, and external IP partners to ensure end-to-end correctness and performance.
• Drive specification, RTL development expectations, validation strategy, and handoff from concept through silicon implementation and bring-up.
• Influence system-level tradeoffs across CPU clusters, accelerators, and memory subsystems.

Requirements

Minimum and preferred technical qualifications for the role.

• Must-have: 5+ years of CPU design experience focused on high-performance computing and AI acceleration.
• Must-have: Practical experience designing hardware for matrix floating-point computation, vector processing, tensor engines, AI accelerators, or machine-learning workloads.
• Must-have: Deep knowledge of CPU architecture, memory hierarchy, data movement, cache coherency, and CPU–accelerator interactions.
• Must-have: Experience defining architectural specifications and leading cross-functional teams from concept through RTL and silicon implementation; hands-on RTL experience with AI model workloads.
• Must-have: Eligibility to access U.S. export-controlled technology; employment may be contingent on U.S. citizenship, permanent residency, or obtaining an export license.
• Nice-to-have: Experience with RISC-V and RVV ecosystems, performance modeling for HPC/AI, low-power design techniques, compiler or software co-design, and silicon bring-up.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.