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CPU Integration / Physical Verification CAD Engineer (Lead/Staff/Sr Staff)

Qualcomm
August 31, 2026
Full-time
On-site
Bengaluru, Karnataka, India
Physical Design Jobs, Level - Senior

Job Title

CPU Integration / Physical Verification CAD Engineer (Lead/Staff/Sr Staff)

Role Summary

The engineer will enable floor-planning, physical design (PD), physical design verification (PDV), and signoff for Qualcomm's Oryon CPU cores. Work focuses on developing, automating and validating place-and-route and signoff flows for high-performance CPU designs at advanced process nodes.

The role sits in the hardware engineering group and collaborates with design, CAD, STA and verification teams to meet timing, power and performance targets.

Experience Level

Senior-level — typically 6+ years of relevant hardware engineering or CAD experience; role advertised at Lead/Staff/Senior Staff levels.

Responsibilities

Primary responsibilities include:

  • Plan and implement floor-planning and physical design for CPU cores.
  • Develop, maintain and run PDV and signoff flows to achieve tapeout-ready designs.
  • Automate place-and-route and verification flows using scripting and tool integration.
  • Perform timing analysis, regression of place-and-route flows, and debug design closure issues.
  • Operate industry-standard P&R and PDV tools to prepare designs for advanced nodes (≤5nm).
  • Collaborate with cross-functional teams to meet performance, power and manufacturability requirements.

Requirements

Must-have:

  • Extensive hands-on experience in development of high-performance chips (design or CAD); typically 6+ years.
  • High proficiency in scripting and programming (Python and Tcl); solid understanding of data structures and algorithms.
  • Proven experience in automation of CAD flows and regression frameworks.
  • Practical experience across physical design tasks: place-and-route, timing analysis, timing sign-off and PDV.
  • Experience with advanced process nodes (5nm or smaller).
  • Strong user of Siemens/Mentor Calibre (PDV) and Cadence Innovus (place-and-route).
  • Track record of managing and regressing place-and-route flows for complex CPU designs.

Nice-to-have:

  • Familiarity with STA tools, C/C++ for tooling, and additional EDA toolsets.

Education Requirements

Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Engineering or a related technical field. Preferred experience levels: Bachelor’s +6 years, Master’s +5 years, PhD +4 years in hardware engineering or related roles — or equivalent practical experience.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-08-29