CPU Hardware Verification (Power Management) Staff Engineer

Job Title

CPU Hardware Verification (Power Management) Staff Engineer

Role Summary

Lead end-to-end verification of CPU co-processor power-management firmware-driven hardware features for SoC platforms. Partner with Firmware, RTL design, emulation and post-silicon teams to define verification strategy, drive signoff, and improve automation and scalability.

Experience Level

Senior. Preferred 10–12+ years of industry experience in CPU/GPU/SoC or complex subsystem verification. Minimum experience expectations vary by degree; see Education Requirements for details.

Responsibilities

Accountable for verification strategy, execution, and cross-functional delivery for CPU power-management features.

• Lead end-to-end verification of firmware-driven CPU co-processor power-management features with focus on power, reliability, and system readiness.
• Architect and implement SystemVerilog/UVM testbenches, transactors, checkers, and verification infrastructure for complex SoC subsystems.
• Plan verification strategy, coverage modeling, regression infrastructure, and drive coverage closure to signoff.
• Define and validate power-management scenarios including DVFS, low-power modes, clock/power transitions, firmware-controlled sequences, power sequencing, and reset flows.
• Debug and perform root-cause analysis across Firmware, RTL, Emulation, and Post-Silicon teams.
• Develop reusable stimulus frameworks, automation, debug utilities, dashboards, and productivity tools to improve scalability.
• Support platform bring-up, feature qualification, HW/FW release validation, and silicon readiness activities.
• Mentor junior engineers and influence verification methodologies and architecture reviews.

Requirements

Key technical must-haves and preferred skills for successful execution.

• Must-have: Extensive SoC/CPU or power-management verification experience and strong SystemVerilog/UVM and testbench architecture skills.
• Must-have: Experience developing NoC transactors, protocol checkers, and verification infrastructure; deep knowledge of AMBA protocols and memory-mapped peripherals.
• Must-have: Strong background in RTL simulation, emulation, waveform analysis, debug methodologies, and coverage closure.
• Must-have: Experience validating DVFS, low-power modes (LPM), idle states, clock/power transitions, power sequencing, and reset flows.
• Must-have: Proficiency in C/C++, SystemVerilog, Python and scripting for automation and data-driven verification workflows.
• Must-have: Strong analytical and debugging skills across hardware, firmware, and system domains; ability to lead technical discussions and influence cross-functional teams.
• Nice-to-have: Power-aware verification, gate-level simulation hands-on experience, CI/CD regression automation, and a track record of delivering verification signoff and mentoring teams.

Education Requirements

Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, or a related engineering field; equivalent practical experience is accepted. Minimum experience expectations tied to degree: Bachelor's +4 years, Master's +3 years, PhD +2 years. Preferred profile: ~10–12+ years of industry experience in CPU/GPU/SoC or complex subsystem verification.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.