CPU Engineering, Director

Job Title

CPU Engineering, Director

Role Summary

Lead CPU physical-design and optimization efforts focused on performance, power, and area (PPA). Work with RTL, architecture, circuits, CAD, process, SoC and post‑silicon teams to drive CPU implementation quality and tapeout readiness.

Experience Level

Senior / Director level. Typical experience expectations are senior: multiple years of ASIC/CPU physical-design experience; the posting indicates senior hires and lists higher preferred experience (see Education Requirements for degree/years detail).

Responsibilities

Technical leadership and cross‑functional coordination focused on CPU physical design and PPA delivery.

• Lead collaboration with RTL, Physical Design, Circuits, CAD, Architecture and Software teams to resolve CPU physical-design challenges.
• Develop and apply physical-design and optimization techniques to meet PPA targets for CPU blocks.
• Coordinate CPU use‑case analysis with Architecture/RTL to propose impactful optimizations.
• Work with CAD tool vendors and internal CAD teams to identify and address optimization issues.
• Partner with block implementation teams, Process, SoC and post‑silicon teams for implementation and correlation activities.

Requirements

Must-have technical skills and experience for this role.

• Experience with synthesis, place & route, and signoff timing/power analysis.
• Knowledge of high‑performance and low‑power implementation techniques.
• Proficiency in scripting (TCL, Python, Perl) for flow automation and analysis.
• Familiarity with industry standard synthesis, P&R and tapeout flows and related CAD tools.
• Strong data‑analysis skills to identify and resolve physical‑design issues and perform pre/post silicon correlation.

Nice-to-have:

• Experience in deep submicron process nodes and CPU PPA optimization.
• Knowledge of library cells and cell‑level optimizations.

Education Requirements

The posting requires a degree in Science, Engineering or a related field. It lists alternative minimums: (a) Bachelor's +8+ years, Master's +7+ years, or PhD +6+ years of ASIC design/verification/validation/integration experience; and a second variant showing lower thresholds: Bachelor's +4+ years, Master's +3+ years, or PhD +2+ years. Preferred: MS in Electrical Engineering with 12+ years of practical experience. Equivalent practical experience may be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.