CPU DV Senior Staff Engineer
SiFiveJob Title
CPU DV Senior Staff Engineer
Role Summary
Lead design verification for complex CPU core microarchitecture and drive DV strategy, architecture validation, and closure for high-performance processors. Work with architecture and design teams to ensure functional correctness, performance, and silicon-quality delivery.
Experience Level
Senior - typically 10+ years of relevant industry experience in CPU design verification.
Responsibilities
Primary responsibilities include ownership of end-to-end verification for CPU core components, development of verification infrastructure, and cross-team validation.
- Own verification of CPU core components: Fetch, Decode, Execute, Memory, Pipeline, Cache, MMU.
- Validate microarchitectural features such as out-of-order execution, branch prediction, cache coherency, virtual memory/paging, RAS and functional safety (Fusa).
- Define test plans from architecture specifications and drive coverage closure.
- Lead verification methodology and execution using SystemVerilog and UVM.
- Develop testbenches, constrained-random tests, scoreboards, checkers, and coverage models (functional and code).
- Drive regressions and debug complex failures across simulation and emulation platforms.
- Collaborate with Architecture & Design teams to validate ISA behavior, corner cases, exceptions, and interrupts; perform ISA-level validation and compliance testing.
Requirements
Must-have technical skills and attributes for the role.
- Extensive experience leading CPU core verification projects and DV strategy.
- Strong SystemVerilog and UVM expertise; experience building robust testbenches and verification IP.
- Proven capability with constrained-random verification, checkers/scoreboards, and functional/code coverage closure.
- Experience debugging across simulation and emulation platforms and driving regressions to closure.
- Deep understanding of CPU microarchitecture concepts (OOO execution, branch prediction, cache coherency, MMU, pipelines).
- Familiarity with ISA behavior (RISC-V, ARM, or x86) for architecture-level validation and compliance.
- Ability to lead cross-functional teams and communicate verification status and risks to stakeholders.
- Must be legally authorized to work in India and able to pass background and export-control checks.
Education Requirements
Bachelor's or Master's degree in Engineering (as stated in the original posting).
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
