CPU Design Verification - Sr Lead Engineer

Job Title

CPU Design Verification - Sr Lead Engineer

Role Summary

Lead post-silicon validation and system-level debugging for CPU interrupt subsystems on ARM-based SoCs. The role owns validation of ARM GIC functionality across CPU, firmware, power-management, hypervisor/kernel and OS interactions.

Experience Level

Senior - preferred 7–16 years of relevant experience. Minimum qualifications allow Bachelor's +2 years, Master's +1 year, or PhD (see Education Requirements).

Responsibilities

Primary accountabilities include planning and executing post-silicon validation for the interrupt controller and coordinating cross-team debug and closure.

• Develop and execute post-silicon validation plans for ARM GICv3/GICv4 and CPU interrupt subsystems.
• Validate GIC components (Distributor, Redistributor, CPU interface, ITS) and interrupt types (SGI, PPI, SPI, LPI).
• Validate interrupt routing, prioritization, masking, preemption, affinity, acknowledgement and EOI behavior.
• Create stress scenarios: high interrupt rates, concurrent interrupts, multi-core routing, SGI broadcasts, interrupt migration and CPU hotplug.
• Validate behavior across CPU power collapse, suspend/resume, reset and DVFS transitions.
• Debug complex issues: lost or stuck interrupts, unexpected routing, latency and incorrect GIC state; correlate register dumps, trace and kernel logs.
• Work with CPU architecture, firmware, kernel, hypervisor, power-management and design teams to root-cause silicon issues.
• Develop automation, stress workloads and regression tests; track coverage, defects and closure status in engineering systems.

Requirements

Must-have technical skills and practical experience required for effective performance in this role. Education details are listed separately in Education Requirements.

• Post-silicon validation or silicon bring-up experience focused on CPU/SoC interrupt subsystems.
• Strong understanding of ARMv8/ARMv9 architecture.
• Strong understanding of ARM GICv3 and GICv4 architectures and relevant registers (GICD, GICR, ICC, ICH, ITS).
• Deep knowledge of interrupt concepts: SGI/PPI/SPI/LPI, affinity and routing, priority/masking/preemption, secure vs non-secure handling, MSI and virtual interrupts (vGIC).
• Familiarity with CPU power states, reset sequences, clock/power collapse and low-power entry/exit behavior.
• Programming/scripting in C/C++, Python and shell for test automation and tools development.
• Hardware/software debugging: register dumps, trace/waveform correlation, kernel logs and crash dumps.
• Experience tracking validation coverage, defects and risk to closure in engineering tracking systems.

Nice-to-have:

• Experience with JTAG/debuggers and SoC debug methodologies.
• Knowledge of virtualization, hypervisors and virtual interrupt handling.
• Experience converting architecture requirements into measurable validation scenarios and coverage metrics.

Education Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering or related field with 2+ years of hardware engineering or related experience; OR Master's degree in those fields with 1+ year of related experience; OR PhD in those fields. (These are the minimum qualification options listed in the source.)

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.