CPU Design Verification Engineer II

Job Title

CPU Design Verification Engineer II

Role Summary

Verify high-performance out-of-order RISC-V CPU cores from RTL bring-up through tapeout. This hands-on role covers block- and core-level verification: building testbench components, generating constrained-random and directed stimulus, closing coverage, and diagnosing hard regression failures.

Work closely with micro-architects and RTL designers and own verification for specific units (e.g. rename/dispatch, issue queues, LSU, MMU/TLB, branch prediction, retire/commit) and core-level scenarios. Position based in Hyderabad, India (onsite).

Experience Level

Mid-level. The role expects approximately 2+ years of pre-silicon functional verification experience; candidates with an MS and strong internships/projects may also be considered.

Responsibilities

Primary responsibilities include:

• Own verification plans for one or more out-of-order core units: extract testable features, define stimulus and coverage requirements, and drive closure.
• Build and extend UVM testbench infrastructure: agents, drivers/monitors, scoreboards, reference models, functional coverage, and SVA assertions.
• Develop constrained-random test generators and directed tests (C/assembly plus SV stimulus) targeting deep pipeline states, speculation, recovery, replay, exception/interrupt injection, memory-ordering and privilege/virtual-memory corner cases.
• Debug regression failures end-to-end: triage waveforms, correlate RTL state to instruction-by-instruction co-simulation mismatches, and reduce failures to minimal reproducers with clear root-cause writeups.
• Drive coverage closure (code, functional, assertion): analyze coverage holes, add stimulus or justified waivers, and report progress toward tapeout milestones.
• Maintain and improve regression health: triage and bucket failure signatures, reduce noise, and improve turnaround and debuggability of the flow.
• Contribute to verification tooling and infrastructure: build/run flows, log parsers, failure-signature classification, and CI integration.
• Review micro-architecture and RTL changes for verification impact and participate in spec reviews.

Requirements

Must-have skills and experience:

• Strong SystemVerilog and UVM knowledge; able to write and extend testbench components independently.
• Solid computer-architecture fundamentals: pipelining, caches, branch prediction, register renaming, out-of-order issue and retirement, and memory consistency basics.
• Proficiency with a simulator (VCS, Questa, or Xcelium) and waveform debug tools (Verdi, Visualizer, or similar); able to debug a failing test from logs to waveform to root cause.
• Bare-metal assembly and C skills; comfortable reading disassembly and reasoning about instruction streams.
• Scripting for automation and analysis: Python and shell/Makefile fluency.
• Experience with version control and code review workflows (Git).

Nice-to-have / preferred:

• Experience verifying out-of-order or superscalar cores.
• Familiarity with RISC-V privileged/unprivileged specs and optional extensions (V, H, A).
• Experience with ISA co-simulation / lockstep golden-model flows and debugging scoreboard mismatches.
• Experience with random instruction-stream generators (e.g. RISCV-DV or equivalent) and extending/constraining generators.
• Formal property verification experience (JasperGold, VC Formal) and exposure to memory-model verification or coherence/ordering checkers.
• Performance verification, emulation/FPGA prototyping, or post-silicon bring-up exposure.

Education Requirements

BS or MS in Electrical/Computer Engineering, Computer Science, or equivalent practical experience. The posting notes MS candidates with strong internship/project experience may be considered; equivalent practical experience is acceptable.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.