CPU Design Verification Engineer

Job Title

CPU Design Verification Engineer

Role Summary

Owner of verification strategy, methodology and execution for out-of-order (OOO) CPU core subsystems. Serve as a technical lead on the design verification (DV) team, driving coverage, sign-off and cross-functional debug.

Work with micro-architecture, RTL, performance and post-silicon teams to ensure correctness, verifiability and successful silicon bring-up.

Experience Level

Mid-level — requires 5+ years of relevant design verification experience.

Responsibilities

Accountable for verification planning, implementation, and sign-off for OOO CPU blocks; lead debug and mentor other engineers.

• Own DV for major OOO core subsystems (front-end, rename/register mapping, issue queues/schedulers, execution units, ROB/retirement, LSU, L1 caches, TLBs, MMU and coherence interfaces).
• Translate ISA and micro-architecture specifications into detailed verification plans and test strategies.
• Architect and implement SystemVerilog/UVM testbenches: reusable environments, agents, monitors, scoreboards and reference models.
• Create constrained-random and targeted stimulus for OOO corner cases (speculation, hazards, reorder stress).
• Define and evolve DV methodology, scenario libraries, and reuse patterns across IPs and projects.
• Define coverage models and sign-off criteria (functional, code, assertion, scenario coverage) and drive coverage closure.
• Develop and maintain SVA assertion sets for key OOO properties and use them in sign-off.
• Lead debug of complex failures including hazards, wrong-path effects, memory ordering and coherence violations, and TLB/MMU corner cases.
• Collaborate with micro-architecture, RTL, performance/modeling and post-silicon teams to resolve issues and align behavior.
• Mentor junior and mid-level DV engineers and provide technical leadership in DV reviews and architecture discussions.

Requirements

Core technical requirements and desirable skills.

• Must-have: Strong hands-on experience with SystemVerilog and UVM; Verilog/RTL experience required.
• Must-have: Proven experience verifying out-of-order CPU cores or major OOO subsystems (front-end, ROB, LSU, pipelines, caches, TLBs).
• Must-have: Experience with constrained-random stimulus, coverage-driven verification, and developing SVA assertions.
• Must-have: Strong debug and root-cause skills for subtle micro-architecture and memory-ordering issues.
• Must-have: Ability to write detailed verification plans and drive block sign-off.
• Nice-to-have: Experience with multi-core coherence, memory models, and post-silicon debug workflows.
• Nice-to-have: Experience contributing to common DV infrastructure and reuse across projects.

Education Requirements

Bachelor's or Master's degree in Engineering is stated (Engineering degree required). The posting specifies 5+ years of experience in addition to the degree. Equivalent practical experience may be considered where applicable.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.