CPU Design Engineer

Job Title

CPU Design Engineer

Role Summary

As a Soft CPU Design Engineer on the IP Engineering team at Altera's San Jose headquarters, you will own micro-architecture, RTL design, and implementation of soft CPU cores optimized for Altera FPGA architectures. The role focuses on architecting processor pipelines, optimizing performance/power/area for programmable logic, and enabling configurable soft cores for customer deployment.

Applicants must be eligible for any required U.S. export authorizations.

Experience Level

Mid-level - typically requires 3+ years of digital design experience focused on CPU/processor RTL design and FPGA implementation.

Responsibilities

Key responsibilities include:

• Micro-architect, design, and implement soft CPU cores in SystemVerilog/Verilog targeting Altera FPGAs.
• Optimize performance, power, and area (PPA) for FPGA-specific resources (ALMs, M20K/MLAB memory blocks, and DSP columns).
• Drive FPGA synthesis, floorplanning, placement constraints, and aggressive timing closure using Altera tool flows.
• Design configurable features such as custom instructions, optional ISA extensions, and variable cache/TCM configurations.
• Collaborate with design verification teams to build simulation environments and perform hardware validation on development boards.

Requirements

Must-have qualifications and skills:

• 3+ years of digital design experience with emphasis on CPU/processor RTL design and FPGA implementation.
• Advanced proficiency in SystemVerilog or Verilog for FPGA synthesis.
• Strong understanding of processor pipeline design, hazard handling, branch prediction, and memory hierarchy.
• Hands-on experience with Altera Quartus Prime Pro and related EDA flows (Platform Designer/Qsys, TimeQuest Timing Analyzer, Signal Tap or equivalents).
• Experience with FPGA synthesis, timing closure, and floorplanning at high frequencies.
• Ability to implement configurable core features and work across verification and validation teams.

Nice-to-have:

• Familiarity with the RISC-V ISA and custom instruction insertion.
• Experience with standard FPGA on-chip interfaces such as Avalon Memory-Mapped/Streaming and AMBA AXI.
• Knowledge of compiler toolchains (GCC, LLVM), assembly programming, and embedded C debugging.
• Proficiency in Python, Tcl, or shell scripting for automation of FPGA compilation and regression workflows.

Education Requirements

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent practical experience.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.