CPU Core Physical Design Engineer

Job Title

CPU Core Physical Design Engineer

Role Summary

Join the US CPU design team to implement physical design for next-generation CPUs from RTL to GDS. You will drive physical implementation, verification/signoff, and optimization of CPU microarchitectures for power, frequency, and area.

The role involves close collaboration with logic, circuit, architecture, design automation teams, and EDA vendors to deliver production-ready CPU designs for AI and high-performance workloads.

Experience Level

Mid-level. See Education Requirements for the degree-and-experience combinations required for initial consideration.

Responsibilities

Primary responsibilities include full physical implementation and signoff of CPU designs:

• Perform physical implementation from RTL to GDS: synthesis, placement & routing, clock tree synthesis, floorplanning, and layout preparation for manufacturing.
• Execute static timing analysis, power/clock distribution design, reliability and power/noise analysis, and timing closure activities.
• Conduct verification and signoff: formal equivalence verification, static timing signoff, reliability verification, power integrity analysis, layout verification (LVS/DRC), electrical rule checking, and structural design checking.
• Analyze implementation results and recommend microarchitecture, logic, or design changes to improve timing, power, or area.
• Collaborate with logic, circuit, architecture, design automation teams, and EDA vendors to develop and enhance tool capabilities and flows.
• Optimize CPU designs for product-level metrics and participate in development of physical design methodologies and flow automation.

Requirements

Must-have technical skills and experience:

• Experience in VLSI circuit design and synthesis (minimum documented experience required).
• Experience with static timing analysis and timing closure.
• Experience in low-power design and multiple power-domain analysis.
• Practical knowledge of physical implementation flow: synthesis, place & route, CTS, floorplanning, power distribution, reliability, and power/noise analysis.
• Signoff and verification experience: formal equivalence, STA signoff, layout verification, ERC/LVS, and structural checks.
• Ability to analyze results and recommend design or microarchitectural changes to improve power, frequency, and area.
• Experience working with EDA vendors and contributing to tool/flow enhancements.
• Strong problem-solving skills and tolerance for ambiguity; effective collaboration across engineering teams.

Nice-to-have:

• Experience with x86 CPU architecture.
• Scripting experience (Tcl, Perl, or Python).

Education Requirements

Required: Bachelor's degree in computer engineering, computer science, electrical/electronic engineering, or any STEM-related field plus 2+ years of relevant experience; OR Master's degree in those fields plus 1+ year of relevant experience. Experience may come from coursework, research, internships, or prior jobs as described in the posting.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.