CPU Core Design Verification Testbench Lead

Job Title

CPU Core Design Verification Testbench Lead

Role Summary

Lead ownership of CPU core-level verification and testbench infrastructure for high-performance out-of-order RISC‑V CPU cores. Collaborate with RTL design, DV, emulation, and post-silicon teams to plan and execute functional verification, regressions, and debug across simulation/emulation/post-silicon flows. This is a hybrid role based out of Santa Clara, CA or Austin, TX.

Experience Level

Senior — typically requires 8+ years in CPU verification, CPU testbench development, or closely related digital design.

Responsibilities

Lead and execute CPU core verification activities and maintain reusable verification infrastructure.

• Lead hands-on CPU core-level testbench development for out-of-order RISC‑V cores.
• Own and evolve CVM-based verification methodology and reusable testbench components.
• Plan and drive functional verification for core features, ISA behavior, and microarchitectural scenarios.
• Develop UVM components, assembly and C/C++ stimulus, and C++ functional models for RISC‑V extensions and un-core components (APIC, IOMMU).
• Debug regressions, close coverage, and improve core/cluster/chip-level testbenches across simulation, emulation, and post-silicon environments.
• Develop Python-based orchestration and AI-assisted tooling for triage and root-cause analysis across logs, waveforms, and verification databases.

Requirements

Key must-have skills and useful additions.

• Must-have: 8+ years in CPU verification or CPU testbench development; proven ownership of CPU core-level testbenches.
• Must-have: Deep understanding of high-performance out-of-order CPU microarchitecture.
• Must-have: Hands-on experience with RTL, simulation, waveform/log-based debug, regression infrastructure, and cross-functional verification workflows including emulation and post-silicon debug.
• Must-have: Experience implementing CVM-based verification methodology and building verification infrastructure (Python orchestration, tooling).
• Nice-to-have: UVM experience and building reusable UVM components; experience creating C/C++ stimulus and C++ functional models.
• Nice-to-have: Familiarity with AI-assisted verification workflows for stimulus generation, debug assistance, and coverage analysis.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.