CPU Core Design Verification Test Generator Lead

Job Title

CPU Core Design Verification Test Generator Lead

Role Summary

Lead development and execution of CPU-focused test generator strategy for high-performance, out-of-order RISC-V cores. You will own generator infrastructure, methodology, and verification strategy across pre-silicon and post-silicon stages and coordinate with design, verification, architecture, emulation, and post-silicon teams.

This position is hybrid, based out of Austin, TX or Santa Clara, CA. Employment may be contingent on eligibility to access U.S. export-controlled technology and could require U.S. citizenship, permanent residency, or an approved license under U.S. export laws.

Experience Level

Senior — typically requires 8+ years of relevant CPU design verification, test generation, or closely related CPU validation experience. Candidates may be assessed across levels during interview.

Responsibilities

Primary responsibilities include owning generator development and verification strategy, delivering stimulus that exercises ISA and microarchitectural corner cases, and guiding a small engineering team while remaining hands-on.

• Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores.
• Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification in pre-silicon and post-silicon flows.
• Develop directed and randomized stimulus targeting architectural corner cases, instruction interactions, and complex CPU behavior.
• Support RISC-V compliance and certification activities: test content, compliance flows, debug, and closure.
• Guide and mentor a small team (approx. 4–5 engineers) while remaining hands-on with implementation, debug, and verification execution.
• Collaborate closely with design, DV, architecture, emulation, and post-silicon teams to drive verification closure.

Requirements

Must-have technical qualifications and demonstrated experience.

• 8+ years in CPU design verification, test generator development, or closely related CPU validation work.
• Proven experience leading development of test generators for x86, ARM, or RISC-V ISA environments.
• Deep understanding of CPU ISA behavior, privileged architecture, and high-performance out-of-order CPU microarchitecture.
• Experience building tools, stimulus, and automation to scale verification across large CPU programs.
• Strong communication skills and experience working across design, DV, architecture, emulation, and post-silicon teams.
• Experience leading or mentoring a small engineering team while remaining hands-on in implementation and debug.
• Nice-to-have: prior involvement in RISC-V certification/compliance workflows, post-silicon debug, or emulation-based verification.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.