CPU Cache Microarchitect/RTL Engineer
AppleJob Title
CPU Cache Microarchitect/RTL Engineer
Role Summary
Join Apple's Silicon Engineering Group to drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems. The role spans micro-architecture exploration, RTL implementation, verification support, and performance correlation to meet power, performance, area, and timing goals.
Experience Level
Mid-level; typically requires 3+ years of relevant industry experience.
Responsibilities
Primary responsibilities include:
- Lead micro-architecture development and produce detailed cache subsystem specifications from high-level exploration.
- Own RTL design: implement, assess, and refine RTL to meet power, performance, area, and timing targets.
- Support verification activities: contribute to testbench development, formal methods, and simulation/emulation efforts.
- Perform performance exploration and correlate architectural choices with performance verification results.
- Collaborate with cross-functional teams (physical design, timing, reliability, testability, power) to deliver design to tape-out.
Requirements
Must-have technical skills and experience:
- Experience with microprocessor architecture and cache subsystems.
- Strong digital logic design skills with awareness of timing and power trade-offs.
- Proficiency in Verilog or VHDL for RTL development.
- Experience with simulators and waveform debugging workflows.
- Familiarity with verification practices including testbench development, formal methods, and simulation/emulation.
Education Requirements
Minimum Bachelor's degree (BS) and 3+ years of relevant industry experience.
About the Company
Company: Apple
Headquarters: Cupertino, California, United States
Apple is a multinational technology company that designs, manufactures, and sells consumer electronics, software, and online services. Known for its innovative products such as the iPhone, Mac computers, and iPad, Apple emphasizes a strong commitment to high-quality design and user experience.
