Collateral Device Engineer

Job Title

Collateral Device Engineer

Role Summary

Join Intel's Manufacturing Development and Customer Engineering (MDCE) Device organization to develop and maintain device collateral and design-rule implementations that connect advanced device technology to high-volume manufacturing. The role supports general-purpose logic CMOS technologies across compute, mobile, mixed-signal, memory controller, and emerging applications.

This position focuses on test chip architectures, scribe line layouts, design-rule waivers, OPC/mask requests, and cross-functional implementation with process integration, yield, device, and design teams.

Experience Level

Level: Senior. Guidance: 7+ years of experience in CMOS device engineering (per minimum qualifications).

Responsibilities

Primary responsibilities include creation, validation, and deployment of device collateral to support characterization, monitoring, and manufacturability of advanced CMOS technologies.

• Design and develop device collateral including test chip architectures and product scribe line layouts for technology characterization and monitoring.
• Collaborate with technology development teams to establish and refine design rules for new device architectures and customize collateral for customer requirements.
• Develop and manage design-rule waiver processes with documentation and risk assessment.
• Create and optimize scribe line monitoring structures to improve yield and process control in high-volume manufacturing.
• Work with manufacturing teams to implement collateral that meets specifications and yield targets.
• Standardize test chip methodologies and scribe line layouts compatible with existing manufacturing platforms.
• Analyze parametric data from test chips and scribe line structures to drive continuous improvement.
• Provide technical guidance on design-rule compliance and waiver justifications to cross-functional teams and customers.
• Monitor industry trends in collateral design, test methodologies, and design-rule evolution.

Requirements

Relevant technical experience and skills. Degree requirements are summarized in the Education Requirements section below.

Must-have:

• Experience with CMOS semiconductor device physics and test chip design for advanced transistor architectures.
• Scribe line layout design and process monitoring structure development for yield enhancement.
• Design-rule development, validation, and waiver management processes.
• DTCO skills including SRAM and standard cell methodologies and cross-functional interfacing with Process Integration, Yield, Device, and Design teams.
• Experience analyzing device parametric data to improve performance and manufacturability.
• Practical experience working with manufacturing teams to implement and qualify device collateral.

Nice-to-have:

• Design Rule Checker (DRC) development and physical verification flow experience.
• Experience in high-volume manufacturing with focus on yield monitoring and process control structures.
• Statistical Process Control (SPC) and advanced data analytics applied to collateral optimization.
• Mask generation experience including Boolean/OPC and OPC/mask request management.
• Hands-on experience with advanced-node test chip design and scribe line optimization for 3nm–16nm FinFETs and sub-3nm GAA FETs.

Education Requirements

Minimum: Master’s degree in Electrical Engineering, Physics, or a related field and 7+ years of CMOS device engineering experience focused on test chip design and collateral development. Preferred: Ph.D. in Electrical Engineering, Physics, or related field with 5+ years of relevant experience. (Degrees and fields specified in the source.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.