Clocking Architect

Job Title

Clocking Architect

Role Summary

Lead the definition, design, and integration of clocking architectures for next-generation FPGA/SoC devices. Own end-to-end clocking strategy from subsystem planning through full-chip integration to ensure robust clock delivery, low skew, and timing/DFT compliance across high-speed protocols and AI accelerator fabrics.

Experience Level

Senior — requires extensive experience; posting specifies 12+ years of industry experience.

Responsibilities

Primary responsibilities include architecture, verification, and cross-functional integration of clocking systems.

• Define full-chip clocking architecture: topology, domain partitioning, frequency planning, and PLL/DLL allocation.
• Produce clocking specifications, diagrams, and constraint documentation for program milestones.
• Architect protocol-specific clock solutions for PCIe, high-speed memory (DDR5/LPDDR5/HBM), Ethernet, SerDes, ARM subsystems, and configuration interfaces.
• Design clocking for ML/AI accelerators: multi-frequency domains, DVFS interactions, and high-bandwidth memory clocking.
• Own CDC architecture and verification: synchronizer strategies, metastability budgets, CDC sign-off, and waiver management.
• Author and validate SDC constraints for functional and DFT modes; coordinate with STA teams for timing closure and sign-off.
• Establish low-power clocking policies, clock gating methodologies, and OCC/DFT scan clock strategies.
• Lead cross-functional reviews, mentor engineers, and represent clocking during architecture and tapeout sign-off.

Requirements

Key must-have technical skills and experience; preferred items listed separately.

Must-have

• 12+ years of experience in physical design, SoC/FPGA design, or clocking architecture with multiple silicon tape-outs at advanced nodes (7nm or below).
• Ownership of full-chip and subsystem-level clocking architecture for complex SoC/FPGA devices.
• Deep practical expertise in PCIe, DDR5/LPDDR5/HBM, ARM interconnects, Ethernet, configuration interfaces, and SerDes clocking.
• Expert CDC architecture experience: full-chip CDC planning, synchronizer selection, metastability analysis, and sign-off.
• Proficiency with CDC verification tools (Synopsys SpyGlass CDC, Cadence JasperGold CDC, Mentor Questa CDC) and waiver processes.
• Expert-level SDC constraint authoring and validation using Synopsys PrimeTime and/or Cadence Tempus.
• Comprehensive DFT clocking experience including scan, ATPG, MBIST/LBIST, and on-chip clock control strategies.
• Experience applying low-power design methodologies (UPF/CPF) in conjunction with clock gating and multi-voltage domains.

Nice-to-have

• FPGA fabric clocking background (PLLs, global/regional networks) and experience with hard IP clocking blocks.
• Experience with formal CDC verification, PLL/DLL characterization, jitter analysis, multi-die/chiplet clocking, and scripting (Tcl/Python) for automation.
• Familiarity with Intel/Altera FPGA families (Stratix, Agilex) or similar architectures.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (as stated). No explicit equivalent-experience clause provided.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.