Chip Lead

Job Title

Chip Lead

Role Summary

Lead end-to-end development of a custom ASIC/chiplet program within Marvell's Custom Compute & Storage (CCS) business unit, focused on datacenter, cloud/AI, carrier and related high-performance markets.

Technical ownership includes architecture, micro-architecture, RTL, verification, DFT, physical implementation and tape-out, with cross-site collaboration and post-silicon debug.

Experience Level

Senior — 16+ years of technical experience; experience as Chip Lead with multiple tape-outs (posting specifies 5+ tapeouts).

Responsibilities

The role owns the full chip program lifecycle and coordinates cross-functional teams to deliver silicon to tape-out and post-silicon validation.

• Lead chip/chiplet program from architecture through tape-out and sign-off.
• Define system and chip architecture and translate system requirements into design specifications.
• Drive micro-architecture and module/SOC design decisions with design teams.
• Ensure adherence to design processes, schedules, and quality metrics across milestones.
• Oversee RTL development and correctness reviews.
• Review and guide verification strategy (functional, coverage-driven, power-aware) and emulation plans, including tape-out gating.
• Coordinate DFT and physical implementation to ensure successful layout and tape-out.
• Lead performance validation and system-level testing for stability, scalability and reliability; support post-silicon debug.
• Address multi-die design challenges (inter-die communication, power, thermal) and interface requirements.
• Mentor and provide technical guidance to junior engineers and cross-functional peers.

Requirements

Key technical qualifications and skills required or strongly preferred.

• Must-have: Proven experience leading RTL-to-GDSII programs and delivering chips to tape-out.
• Must-have: Strong background in RTL design, verification methodologies, and physical design flow.
• Must-have: Proficiency with scripting (Perl, Python) and common EDA tools.
• Must-have: Solid understanding of system/processor architecture, advanced memory and high-speed I/O technologies.
• Must-have: Experience in multi-die solutions and addressing inter-die, power and thermal issues.
• Must-have: Experience designing chips for datacenter/high-performance applications with emphasis on performance and power optimization.
• Must-have: Strong communication, problem-solving, leadership and cross-functional collaboration skills.
• Nice-to-have: Prior work on CXL, AI/Cloud accelerator platforms or similar datacenter interconnect technologies.
• Candidates must not use AI-assisted tools during interviews, per the hiring process guidelines.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Science/Engineering, or a closely related technical field (as stated in the posting).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.