CAD and PPA Methodology Engineer
QualcommJob Title
CAD and PPA Methodology Engineer
Role Summary
The engineer will develop and deploy CAD flows, methodologies and algorithms to improve power, performance and area (PPA) for GPU cores. The role works within the Graphics ASIC team and partners with microarchitecture, implementation, power, sign-off and post-silicon teams to drive PPA improvements.
Experience Level
Mid-level — typically 3–7 years of relevant ASIC/CAD or methodology experience; 5–7 years preferred for methodology leadership on complex GPU projects.
Responsibilities
Deliver methodology and flow improvements and drive cross-functional execution to improve PPA on GPU cores.
- Design, implement and validate CAD flows and PPA-oriented methodologies from RTL to GDSII.
- Collaborate with microarchitecture, implementation, power and sign-off teams to translate PPA goals into design constraints and fixes.
- Perform RTL synthesis, static timing analysis, formal checks, physical design tuning and ECO generation/verification.
- Identify bottlenecks and propose tool/process improvements to meet power, timing and area targets.
- Develop scripts and automation to integrate and scale methodologies across designs.
- Document methodology, run reviews, and support post-silicon analysis where needed.
Requirements
Key technical skills and experience expected for successful candidates.
Must-have
- Practical understanding of digital RTL and ASIC design flow: synthesis, STA, formal verification, physical design and ECO processes.
- Experience developing methodologies or flows focused on improving power, performance and area for complex digital designs.
- Familiarity with Verilog/SystemVerilog and RTL-to-GDS implementation concepts (constraints, clocking, interfaces).
- Ability to analyze trade-offs among power, performance and area and drive engineering decisions.
- Proficiency with scripting/automation (Python, Perl, Tcl, UNIX shell) for tool integration and flow automation.
- Strong communication and collaboration skills to work with multiple functional teams.
Nice-to-have
- Experience delivering GPU cores or other high-performance processors from RTL to GDSII.
- Familiarity with Synopsys toolflow (Fusion Compiler, RTL-Architect, PrimeTime, PrimePower, Prime Closure) and clock tree optimization techniques.
- Experience with ECO methodologies and formal netlist checks between RTL and netlist.
Education Requirements
Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering or a related field plus 4+ years of relevant engineering experience; OR Master's degree in those fields plus 3+ years of relevant experience; OR PhD in those fields plus 2+ years of relevant experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
