Job Title
Automotive SoC Verification Engineer (SystemVerilog/UVM)
Role Summary
Black Sesame Technologies is hiring an engineer to develop and maintain verification environments for automotive SoCs. The role focuses on SystemVerilog/UVM test development, running regressions, and contributing to formal property verification (FPV) strategies.
The position requires collaboration with RTL designers, software, and systems engineers to ensure functional correctness and coverage for next-generation automotive SoCs.
Experience Level
Mid-level. Years-of-experience guidance not specified.
Responsibilities
Primary responsibilities include verification environment development, test execution, and cross-team debugging.
- Design, implement, and maintain SystemVerilog/UVM verification environments and testbenches.
- Create and run directed and constrained-random tests; manage regression runs.
- Analyze functional coverage and close verification gaps.
- Debug RTL and verification failures; isolate and document root causes.
- Contribute to FPV strategies and formal verification efforts.
- Collaborate with RTL designers, software, and system teams to resolve issues.
- Maintain verification documentation and regression infrastructure.
Requirements
Required technical skills and preferred qualifications.
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Must-have: Practical experience developing and running SystemVerilog/UVM testbenches.
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Must-have: Experience in SoC or complex IP verification, including regression and coverage analysis.
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Must-have: Familiarity with FPV concepts or demonstrated contribution to formal verification strategies.
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Nice-to-have: Experience with mainstream simulators and verification toolchains (e.g., VCS, Questa, Xcelium).
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Nice-to-have: Scripting skills for automation (Python, Tcl, Perl) and experience with CI/version-control driven regressions.
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Nice-to-have: Exposure to automotive development practices or safety standards (e.g., ISO 26262).
Education Requirements
Not specified.
About the Company
Company: Beacon Industries
Technology/engineering company focused on analog and mixed-signal integrated circuit design and custom IC layout (SerDes, SRAM, high-speed interfaces), using Synopsys/Cadence EDA tools for design, simulation, verification, and silicon validation.

Date Posted: 2026-08-17