Automotive SoC Verification Engineer (SystemVerilog/UVM)

Job Title

Automotive SoC Verification Engineer (SystemVerilog/UVM)

Role Summary

The Engineer, Design Verification develops and maintains verification environments for automotive system-on-chip (SoC) projects. The role focuses on building SystemVerilog/UVM testbenches and verification platforms to validate RTL functionality and coverage.

Hands-on position collaborating with RTL designers, architects, and validation teams to deliver high-quality verification results for next-generation automotive SoCs.

Experience Level

Mid-level. Years of experience not specified.

Responsibilities

Primary responsibilities include:

• Design, implement, and maintain SystemVerilog/UVM verification environments and testbenches.
• Plan and execute verification tests, run regressions, and analyze simulation results.
• Debug functional failures and work with RTL teams to resolve issues.
• Contribute to FPV (formal/property) strategy and verification planning.
• Collaborate with cross-functional engineering teams to close coverage and improve verification infrastructure.
• Automate test execution and maintain verification documentation.

Requirements

Must-have and preferred qualifications:

• Must-have: Practical experience with SystemVerilog and UVM in SoC or complex IP verification.
• Must-have: Experience developing verification environments and executing coverage-driven tests.
• Must-have: Strong debugging skills and ability to analyze simulation output.
• Nice-to-have: Experience with automotive SoCs, industry protocols, or domain-specific validation.
• Nice-to-have: Familiarity with verification tools and simulators, scripting (Python/Tcl), and coverage closure methodologies.
• Nice-to-have: Experience with formal/property verification tools and strategies.

Education Requirements

Not specified.

About the Company

Company: Beacon Industries

Technology/engineering company focused on analog and mixed-signal integrated circuit design and custom IC layout (SerDes, SRAM, high-speed interfaces), using Synopsys/Cadence EDA tools for design, simulation, verification, and silicon validation.