Automotive SoC Verification Engineer (SystemVerilog/UVM)
DensityAIJob Title
Automotive SoC Verification Engineer (SystemVerilog/UVM)
Role Summary
Design Verification engineer for automotive SoCs responsible for building verification environments, executing SystemVerilog/UVM tests, and supporting verification strategies. The role involves hands-on verification work and cross-functional collaboration with RTL, firmware, and validation teams.
Experience Level
Mid-level. Years of experience not specified.
Responsibilities
Key responsibilities include:
- Develop and maintain SystemVerilog/UVM verification environments and testbenches for SoC blocks and full-chip scenarios.
- Write and execute directed and randomized tests; analyze results and debug failures.
- Contribute to formal and functional verification strategies and coverage closure.
- Create regression suites and integrate tests into simulation/CI flows.
- Work with RTL designers, firmware, and validation teams to identify and resolve issues.
- Document verification plans, test results, and defects.
Requirements
Must-have skills and experience:
- Practical experience with SystemVerilog and UVM for SoC or block-level verification.
- Experience in design verification for SoC or semiconductor products.
- Familiarity with verification methodologies, testing, and defect tracking.
- Attention to detail and ability to work in a fast-paced engineering environment.
Nice-to-have:
- Automotive domain experience.
Education Requirements
Not specified.
About the Company
Company: DensityAI
Headquarters: Mountain View, CA, United States
DensityAI is a semiconductor company focused on developing advanced silicon and multi-die packaged chips, with expertise in design-for-test, verification, and production test for high-performance and AI applications.
