Austin Hiring Event - Senior Physical Design Engineer

Job Title

Austin Hiring Event - Senior Physical Design Engineer

Role Summary

Senior physical design engineer on Marvell's Processor/ASIC team responsible for block-level place-and-route and design methodology for high-performance processor chips targeted at server and networking applications.

Work on-site in Austin, TX with a global team to implement physical design flows, run sign-off checks, and develop methodology to improve design quality and turnaround.

Experience Level

Senior — experienced engineer. (No explicit years of experience listed.)

Responsibilities

Contribute to physical design and methodology for complex, advanced-node ASICs; ensure robust sign-off of block-level designs.

• Perform block-level place-and-route (PnR) and drive PNR flows from RTL through layout.
• Run static timing analysis and triage timing issues using industry STA tools.
• Perform power integrity (EM/IR) analysis and address IR/EM violations.
• Execute physical verification sign-off checks and resolve DRC/LVS issues.
• Review completed tool runs, identify errors, and create optimizations to improve results and turnaround.
• Develop and refine physical-design methodology and flows to increase efficiency and robustness.
• Collaborate with synthesis, verification, and backend teams to deliver tapeout-quality blocks.

Requirements

Key technical skills and eligibility requirements. Degree information is summarized separately below.

• Must have block-level physical design experience for advanced CMOS nodes (e.g., 7nm, 5nm, or below).
• Proven hands-on experience with industry physical-design EDA tools such as Cadence Genus and Innovus, and Synopsys Design Compiler, IC Compiler, or Fusion Compiler.
• Familiarity with static timing analysis tools and power/EM analysis workflows; ability to interpret tool reports and implement fixes.
• Experience reviewing and interpreting sign-off runs and implementing optimizations to meet timing, power, and area targets.
• Good troubleshooting skills and willingness to learn new flows and mentor/receive mentorship within the team.
• Must be eligible to access export-controlled technology; non-U.S. citizens may be subject to export license review prior to employment.
• Nice-to-have: experience with STA tools (Tempus, PrimeTime), EM/IR tools (Voltus, PrimeRail), and physical/formal verification tools (Calibre, LEC, Formality).

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related technical field, or equivalent practical work experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.