ATE Test Engineer

Job Title

ATE Test Engineer

Role Summary

Join the semiconductor test engineering team in Valbonne (Sophia Antipolis), France to develop, validate, and optimize Automated Test Equipment (ATE) solutions for device characterization and product qualification. You will work across design, product, and validation teams in France, India, and the United States and support activities from early test development and silicon bring-up to production ramp and customer qualification.

Experience Level

Mid-level. The role targets junior engineers with approximately 3 to 6 years of relevant semiconductor test or validation experience.

Responsibilities

The main responsibilities include development and execution of ATE test programs, silicon bring-up and characterization, debugging, and collaboration with cross-functional teams.

• Develop, debug, and maintain ATE test programs for wafer sort and final test.
• Convert design test patterns (VCD, wgl, STIL) into ATE-compatible formats.
• Generate and execute functional, parametric, characterization, and debug test programs.
• Define test strategy, coverage, and pass/fail limits aligned with design specifications.
• Perform silicon bring-up, characterization, shmoo analysis, and device debug.
• Collect, process, and analyze ATE data using scripts and tooling.
• Collaborate with design, IP, and product teams to debug failing devices.
• Contribute to test methodology, loadboard and hardware interface development as needed.
• Optimize test time, cost, and quality; support production ramp and customer qualification.
• Use lab equipment (oscilloscopes, curve tracers) for validation and debug.

Requirements

Must-have technical skills and experience required to perform the role.

• 3 to 6 years of hands-on experience in semiconductor test, validation, or related engineering roles.
• Understanding of semiconductor device testing and characterization methodologies.
• Programming experience in one or more languages such as C, C++, Python, or Java for test automation and data processing.
• Experience with data analysis, troubleshooting, and debugging techniques.
• Familiarity with digital electronics and semiconductor fundamentals.
• Ability to work in multicultural, cross-functional teams and communicate in English.

Nice-to-have:

• Experience with ATE platforms (for example, Advantest 93K, Teradyne).
• Basic knowledge of DFT and functional test methodologies.
• Experience with hardware design (loadboards, packages) or semiconductor manufacturing processes.
• Background in digital, mixed-signal, or memory testing (CMOS, DRAM, SRAM).

Education Requirements

Master's degree in Electrical Engineering, Microelectronics, Electronics, Computer Engineering, or a related technical discipline is specified. The posting targets junior engineers with 3 to 6 years of experience; candidates with equivalent practical experience may be considered based on skill set.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.