ATE Test Engineer

Job Title

ATE Test Engineer

Role Summary

As an ATE Test Engineer on the semiconductor test engineering team in Valbonne (Sophia Antipolis), you will develop, validate, and optimize automated test equipment (ATE) solutions for wafer sort and final test across the product lifecycle. You will support silicon bring-up, production ramp-up, and customer qualification while collaborating with design, product, and validation teams across France, India, and the United States.

Experience Level

Mid-level. Targeted experience: 3–6 years.

Responsibilities

Typical responsibilities include:

• Develop, debug, and maintain ATE test programs for wafer sort and final test.
• Convert design test patterns (VCD, wgl, STIL) into ATE-compatible formats.
• Create and execute functional, parametric, characterization, and debug test programs; define test strategy, coverage, and limits.
• Perform silicon bring-up, characterization, and shmoo analysis.
• Collect, process, and analyze ATE data using scripts and tools.
• Debug failing devices in collaboration with design, IP, and product engineering teams.
• Contribute to test methodologies and best practices; optimize test time, cost, and quality.
• Use lab equipment (oscilloscopes, curve tracers) for validation and debug; support loadboard and hardware interface development when needed.

Requirements

Must-have technical skills and abilities:

• Understanding of semiconductor device testing and characterization methodologies.
• Programming experience in one or more languages: C, C++, Python, or Java.
• Experience with data analysis, troubleshooting, and debugging techniques.
• Familiarity with digital electronics and semiconductor fundamentals.
• Ability to work effectively in multicultural, cross-functional teams and communicate in English.
• Good analytical and problem-solving skills; a curious mindset and willingness to learn.

Nice-to-have:

• First experience with ATE platforms (e.g., Advantest 93K, Teradyne).
• Basic knowledge of DFT and functional test methodologies or memory testing (CMOS, DRAM, SRAM).
• Experience with hardware design (loadboards, packages) or familiarity with semiconductor manufacturing processes.

Education Requirements

Master's degree in Electrical Engineering, Microelectronics, Electronics, Computer Engineering, or a related technical discipline.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.