Associate Staff/Staff Implementation Design Engineer

Job Title

Associate Staff/Staff Implementation Design Engineer

Role Summary

Lead and execute back-end (BE) implementation for high-performance SoCs, owning synthesis, static timing analysis (STA), logic equivalence, low-power/UPF checks, and timing sign-off. Work cross-functionally with front-end RTL, DFT, place-and-route, verification, and packaging teams to ensure timing closure and PPA optimization.

This is a hands-on technical lead role responsible for driving methodology improvements and mentoring junior engineers.

Experience Level

Senior — 9–10 years of relevant ASIC physical design and implementation experience.

Responsibilities

Primary responsibilities include end-to-end physical design ownership and timing sign-off:

• Develop, manage, and validate timing constraints for RTL-to-GDSII flows in collaboration with design and DFT teams.
• Execute STA for digital blocks and top-level designs and interpret timing reports.
• Create and implement timing ECOs to resolve critical paths and close timing.
• Generate CTS specifications with PnR engineers and support clock tree synthesis.
• Run logical equivalence checks and support sign-off verification.
• Develop and validate UPF/low-power implementation and checks for power management.
• Perform CDC, false-path, and multicycle path checks.
• Drive EDA tool flow automation and methodology enhancements for scalability.
• Own and optimize power, performance, and area (PPA) metrics for assigned designs.
• Lead small teams, mentor junior engineers, and coordinate across multi-site teams.

Requirements

Must-have technical skills and experience; preferred items noted separately.

• 9–10 years of ASIC physical design and implementation experience, including timing sign-off.
• Hands-on experience with industry EDA tools such as Cadence (Genus, Innovus, Tempus, LEC, CLP) or Synopsys (ICC2, Fusion Compiler, PrimeTime).
• Strong background in synthesis, constraints development, timing analysis, margins, and timing fixing.
• Knowledge of low-power design techniques (UPF/CPF, power gating, DVFS) and low-power checks.
• Solid understanding of architecture-to-GDSII flows and sign-off criteria (timing, IR drop, EM, DRC/LVS).
• Experience with multi-clock, multi-voltage, and hierarchical designs.
• Excellent problem-solving and communication skills.
• Nice to have: automation skills (Perl/Tcl/Python), familiarity with DFT, floorplanning, PnR, physical verification, and prior experience leading small teams.

Education Requirements

Bachelor's or Master’s degree in Electrical/Electronic Engineering, VLSI, ECE, EEE, or a related technical field (as stated). No certifications were specified.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.