Associate Staff Modem Verification Engineer

Job Title

Associate Staff Modem Verification Engineer

Role Summary

Join the Design Verification team responsible for verification of wireless modem IP, subsystems, and SoCs. The role focuses on PHY/MAC functionality, modem datapaths and control, and digital/RF interfaces, working closely with architecture, RTL design, DSP, firmware, RF, and post-silicon teams.

The engineer will develop verification plans, build reusable UVM environments, create coverage-driven tests, debug complex integration failures, and drive features from specification through sign-off.

Experience Level

Mid-level (typically 5–8 years of ASIC/SoC design verification experience).

Responsibilities

Primary responsibilities include verification planning, environment development, test creation, debugging, and cross-team coordination.

• Develop and execute verification plans for modem IP, subsystems, and SoCs with defined feature, coverage, and sign-off criteria.
• Build, enhance, and maintain SystemVerilog/UVM verification environments (agents, sequences, scoreboards, assertions, coverage).
• Create directed and constrained-random tests and drive functional and code coverage closure via gap analysis.
• Verify datapaths, control logic, PHY/MAC interactions, digital/RF interfaces, registers, buses, memories, clocks, resets, and interrupts.
• Run and debug RTL and gate-level regressions; perform root-cause analysis of protocol, timing, and integration failures.
• Own features from specification review through verification closure; communicate status, risks, and dependencies.
• Improve productivity through scripting, regression automation, CI, reusable infrastructure, and metrics-driven debug.
• Participate in architecture, design, test-plan, and coverage reviews; mentor junior engineers and share best practices.

Requirements

Must-have technical skills and experience for immediate contribution.

• 5–8 years (typical) of hands-on ASIC/SoC design verification experience, with consideration for stronger candidates outside this range.
• Strong SystemVerilog and UVM experience, including constrained-random verification, SVA, and functional coverage.
• Experience verifying wireless modem or connectivity IP at block, subsystem, or SoC level.
• Good understanding of PHY/MAC architecture, digital design fundamentals, SoC architecture, and digital/RF integration.
• Proven debug skills with tools such as Verdi, DVE, or SimVision and simulators like VCS, Xcelium, or Questa.
• Proficiency in C/C++ and scripting (Python, Tcl, or Shell) for test development, modeling, and automation.
• Ability to work independently, solve cross-layer issues, and communicate effectively with distributed cross-functional teams.
• Familiarity with regression management, continuous integration, and metrics-driven verification improvements.

Education Requirements

B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Computer Engineering, VLSI, or a related field.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.