ASICS Design Engineer (Senior to Staff)

Job Title

ASICS Design Engineer (Senior to Staff)

Role Summary

Design and deliver RTL and micro-architectures for Ethernet switching subsystems on networking ASICs. The role focuses on RTL implementation, synthesis, timing closure, SoC integration, performance tuning, and cross-team debugging to support chip bring-up.

Works on complex datapath and control logic, drives subsystem integration and optimization, and mentors junior engineers.

Experience Level

Senior to Staff level. Typical background: 2–10 years of ASIC design experience in networking or merchant silicon.

Responsibilities

The position owns design, integration and delivery of Ethernet switch subsystems within an SoC.

• Implement RTL design, synthesis, and timing closure for networking datapath and control logic.
• Participate in SoC integration with focus on Ethernet switch subsystems and subsystem integration.
• Lead micro-architecture and RTL design for networking blocks (forwarding engine, parser, traffic manager).
• Drive performance tuning, power optimization, and architecture-aligned implementation.
• Debug functional and performance issues across design, verification, and validation teams.
• Collaborate with architecture, firmware, and validation teams to support chip bring-up.
• Mentor junior engineers and promote engineering best practices.

Requirements

Key technical skills and abilities required or strongly preferred.

• Must have: Proven ASIC design experience with logic design, RTL coding, verification, synthesis, timing closure, and physical design flow.
• Must have: Strong expertise in front-end ASIC design flow (RTL, simulation, static timing analysis, integration).
• Must have: Familiarity with Ethernet switching concepts (L2/L3 forwarding, bridging, routing), packet processing pipelines, and basic QoS (queuing, scheduling).
• Must have: Hands-on experience with Ethernet switching/networking ASICs (packet classification/forwarding pipelines, buffer management, QoS mechanisms) and protocols such as Ethernet, VLAN, TCP/IP, and tunneling.
• Must have: Strong debugging and system-level problem-solving skills; ability to independently drive complex design tasks under tight schedules.
• Nice to have: Familiarity with AXI/NoC, PCIe, or other high-speed interfaces.
• Nice to have: Scripting experience (C/C++, Tcl, Perl) for automation and debug.
• Fluent written and spoken Chinese and English.

Education Requirements

Degrees in Science, Engineering or related fields are specified: Bachelor's, Master's, or PhD (MS in Electrical Engineering noted as preferred). Minimum experience expectations tied to degree: Bachelor's +4 years, Master's +3 years, PhD +2 years.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.