ASICS Arch VI Engineer, Senior to Sr Staff

Job Title

ASICS Arch VI Engineer, Senior to Sr Staff

Role Summary

Execute pre-silicon and post-silicon validation, bring-up, debug, and system-level verification for packet-processing ASIC forwarding plane (PPE). Work within the ASICS Engineering validation team to define and own validation strategy, test plans, and automation to ensure functional correctness, performance, stability, and protocol consistency.

Experience Level

Senior (Senior to Sr. Staff). Typical experience expectation: mid-to-senior level engineering with multiple years of ASIC validation/verification/integration experience (see Education Requirements for degree/years guidance).

Responsibilities

Primary duties include validation strategy, bring-up, test execution, and coordination across teams.

• Plan and execute pre-silicon and post-silicon validation, bring-up, feature enablement, and regression testing for PPE forwarding functions.
• Develop, maintain, and run validation content covering forwarding features and representative use cases.
• Perform PPE performance validation across packet sizes and stress patterns; document results and identify gaps versus targets.
• Conduct protocol consistency testing with real protocol implementations and provide actionable debug evidence for inconsistencies.
• Lead emulation- and silicon-based bring-up; coordinate issue triage and root-cause isolation with software, hardware, design, DV, and customer teams.
• Develop and maintain validation infrastructure and automation (regressions, dashboards, reusable test frameworks) to unify model/emulation/chip validation.
• Feed system-level findings back into specifications, DV test intent, and debug hooks to improve quality early in the lifecycle.
• Mentor and coach team members; provide technical leadership without direct reports when required.

Requirements

Must-have technical skills and professional competencies.

• Hands-on experience with emulation-based validation and/or post-silicon board-based validation, bring-up, and stability/performance testing.
• Practical experience in packet-based testing and debug: traffic generation, packet capture/analysis, and counters/statistics interpretation for forwarding and performance validation.
• Scripting and tooling experience for validation automation and lab debug (examples: C, Perl, TCL, makefiles, shell scripts).
• Familiarity with ASIC development and system/SoC networking datapath concepts.
• Experience building automation infrastructure and validation processes (regressions, dashboards, reusable frameworks).
• Strong analytical, communication, and decision-making skills; organized and able to manage multiple parallel tasks under tight schedules.
• Ability to mentor and develop others; collaborate effectively across teams.
• Fluent in Chinese and English, both written and spoken.

Education Requirements

MS or BS in Electrical Engineering, Computer Science, or related field (MS preferred). Minimum qualifications specify: Bachelor's degree plus 6+ years relevant ASIC design/verification/validation/integration experience; OR Master's degree plus 5+ years; OR PhD plus 4+ years. Equivalent practical experience is accepted where stated in the minimum qualifications.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.