ASIC Verification Staff Engineer
SynopsysJob Title
ASIC Verification Staff Engineer
Role Summary
Senior verification engineer responsible for architecting and implementing SystemVerilog/HVL-based verification environments and driving verification closure for DesignWare IP cores. The role sits on the DesignWare IP Verification R&D team and collaborates with RTL designers and global verification teams to deliver production-quality IP for commercial, enterprise, and automotive applications.
Experience Level
Senior - typically 5+ years of relevant ASIC or IP verification experience.
Responsibilities
Primary responsibilities focus on verification environment development, test planning, and cross-team collaboration to meet quality metrics and schedules.
- Specify, architect, implement, and maintain HVL/SystemVerilog verification environments and testbenches.
- Develop and execute comprehensive test plans covering unit- and system-level requirements.
- Design test cases and functional coverage models; perform coverage analysis and manage regression suites.
- Debug failing tests, root-cause issues with RTL and verification infrastructure, and drive fixes to closure.
- Automate verification flows using scripting to improve throughput and reproducibility.
- Collaborate with RTL designers and distributed verification teams to integrate verification and resolve issues.
- Contribute to verification methodology improvements, VIP development, and adoption of formal techniques where appropriate.
Requirements
Core technical requirements and preferred skills.
- Must-have: Strong SystemVerilog/HVL experience and hands-on expertise building verification environments and testbenches.
- Must-have: Practical experience with industry simulators and debugging tools (examples: VCS, NC, MTI).
- Must-have: Proficiency with verification methodologies (UVM/OVM/VMM) and coverage-driven verification.
- Must-have: Scripting proficiency to automate flows (Perl, TCL, Python).
- Must-have: Familiarity with common protocols: MIPI-I3C, UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.
- Nice-to-have: Experience with VIP development, formal verification exposure, Verilog/HDL experience.
- Nice-to-have: Mentoring experience and ability to contribute to cross-site engineering processes and quality metrics.
Education Requirements
Bachelor of Science in Electrical/Electronics Engineering (BSEE) with ~5+ years relevant ASIC/IP verification experience, or Master of Science in Electrical/Electronics Engineering (MSEE) with ~3+ years relevant ASIC/IP verification experience (as stated in the source).
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
