ASIC Verification - Senior Staff Engineer
SynopsysJob Title
ASIC Verification - Senior Staff Engineer
Role Summary
Senior verification engineer responsible for architecting and implementing verification environments and testbenches for DesignWare IP cores. Work within a global DesignWare IP Verification R&D team to deliver robust IP for commercial, enterprise, and automotive applications.
Focus on functional verification, coverage-driven methodologies, regression management, and automation to meet quality and time-to-market goals.
Experience Level
Senior. Typically requires approximately 6–8+ years of relevant ASIC/IP verification experience.
Responsibilities
Design and execute verification strategies and deliverables for IP cores.
- Specify, architect, and implement SystemVerilog-based verification environments and testbenches.
- Develop and run test plans covering unit and system-level requirements; create test cases and functional coverage models.
- Perform functional coverage analysis and manage regression suites to meet quality metrics.
- Debug complex RTL and verification issues; collaborate with RTL designers and global verification teams to achieve closure.
- Automate verification flows using scripting (Perl, TCL, Python) to improve productivity.
- Contribute to verification methodology improvements, VIP development, and formal verification initiatives.
- Mentor junior engineers and support multi-site R&D collaboration.
Requirements
Core technical skills and practical experience required for the role.
- Expertise in SystemVerilog and HVL-based verification environment development.
- Hands-on experience with industry simulators and debugging tools (examples: VCS, NC, MTI).
- Proficiency with verification methodologies such as UVM, OVM, or VMM.
- Strong familiarity with protocols (examples: MIPI-I3C, UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB).
- Experience with functional coverage-driven verification and meeting quality metric goals.
- Scripting skills for automation (Perl, TCL, Python); familiarity with Verilog HDL.
- Good communication, debugging, and cross-functional teamwork skills.
- Nice-to-have: experience with formal verification and VIP development.
Education Requirements
Degree guidance in posting: BSEE (with ~8+ years relevant experience) or MSEE (~6+ years relevant experience) in Electrical/Electronics Engineering or a closely related technical field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
