ASIC Verification Engineer with UVM Expertise
Lumiere SystemsJob Title
ASIC Verification Engineer with UVM Expertise
Role Summary
Lead development and execution of verification infrastructure and test plans for digital ASIC designs. Work with a distributed engineering team to implement UVM-based generators, self-checking tests, and verification flows that validate functionality and protocol compliance.
Experience Level
Senior — requires 8+ years of ASIC verification experience.
Responsibilities
Primary responsibilities include building verification infrastructure and validating ASIC designs.
- Lead development of ASIC verification infrastructure and flows.
- Create UVM-based protocol generators, checkers, and reusable verification components.
- Develop and execute detailed ASIC test plans and verification scenarios.
- Implement self-checking tests and automation to ensure design robustness.
- Collaborate with distributed design and verification teams to diagnose and resolve issues.
Requirements
Must-have technical skills and experience.
- 8+ years of ASIC verification experience (system-level and block-level).
- Proficient in SystemVerilog and verification using UVM.
- Experience with Python for testbench automation and tooling.
- Strong understanding of verification methodologies and self-checking test design.
- Effective written and verbal communication skills for distributed teams.
Education Requirements
Bachelor's degree in Computer Science or Electrical Engineering.
About the Company
Company: Lumiere Systems
Engineering services firm specializing in semiconductor and ASIC design and verification for ARM-based SoCs. Engages in full verification lifecycle (UVM/SystemVerilog, formal, gate-level simulation) and collaborates with global verification teams and client partners.
