ASIC Verification Engineer with UVM Expertise

Job Title

ASIC Verification Engineer with UVM Expertise

Role Summary

Lead verification efforts for digital ASIC designs, focusing on building verification infrastructure, UVM-based generators, and self-checking tests. Collaborate with a distributed engineering team to validate functionality and standards compliance.

Experience Level

Senior-level — requires 8+ years of verification experience in ASIC design.

Responsibilities

Primary duties include developing verification infrastructure and executing comprehensive test plans:

• Lead development of ASIC verification infrastructure and frameworks.
• Create UVM-based protocol generators and checkers.
• Develop and execute detailed ASIC test plans and regression suites.
• Define and implement self-checking, coverage-driven tests for designs.
• Work with a distributed team to diagnose and resolve complex design issues.

Requirements

Must-have technical skills and team capabilities:

• 8+ years of verification experience in ASIC design.
• Proficient in SystemVerilog and Python.
• Strong understanding and practical use of UVM and verification methodologies.
• Experience developing self-checking tests and validators.
• Effective communication skills for working with distributed teams.

Education Requirements

Bachelor's degree in Computer Science or Electrical Engineering specified. (No alternative equivalent-experience language provided.)

About the Company

Company: Myticas Consulting

Technology consulting and staffing firm that recruits engineering and IT professionals. Focuses on placing and supporting roles in ASIC/semiconductor design, embedded systems, software engineering, and related technical disciplines through contract and permanent placements.