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ASIC Verification Engineer

Capgemini
July 21, 2026
Full-time
Remote
Worldwide
$76,200 - $187,740 USD yearly
Verification Jobs, Level - Mid-Career

Job Title

ASIC Verification Engineer

Role Summary

Individual-contributor verification engineer responsible for verification of ARM-related IP blocks (CPU Cortex-A v9, GPU Mali, Debug CoreSight/CSS600) as part of Capgemini Engineering. This is a 100% remote role focused on delivering RTL verification, coverage analysis, and gate-level validation for IP blocks and subsystems.

Experience Level

Mid-level (expectation: 5+ years of ASIC verification experience).

Responsibilities

Primary ownership of verification activities for core IP blocks across the project lifecycle.

  • Develop and execute verification plans, test cases, and UVM/SystemVerilog environments for block-level verification.
  • Perform constrained-random verification, assertions, coverage collection and coverage analysis.
  • Debug RTL issues, perform gate-level simulation (GLS), and validate fixes.
  • Design and implement C-based tests to configure and exercise ARM IPs and reuse vendor-provided test benches where applicable.
  • Participate in specification and architectural reviews; provide design-for-test and verification feedback to design teams.
  • Collaborate with the global verification team to improve processes, methodologies, and verification quality.

Requirements

Must-have technical skills and experience; followed by concise nice-to-have items.

  • 5+ years hands-on ASIC verification experience using SystemVerilog/UVM and industry-standard methodologies.
  • Experience with formal verification, constrained-random testing, assertions, and coverage-driven verification.
  • Gate-level simulation experience and coverage analysis capability.
  • Strong practical experience with ARM-related IP (Cortex-A v9, Mali GPU, CoreSight/CSS600 or similar).
  • Experience writing C-based tests to configure/test ARM IPs and integrating/reusing manufacturer test benches.

Nice-to-have:

  • Experience creating UVM test environments reusable at subsystem level.
  • Ability to read RTL (SystemVerilog, Verilog, VHDL).
  • Experience with revision control, CI/CD pipelines for verification, and automated regression frameworks.
  • Strong documentation, communication, and cross-team collaboration skills.

Education Requirements

Not specified.


About the Company

Company: Capgemini

Headquarters: Paris, France

Global consulting, technology and engineering services firm offering digital and business transformation, cloud, AI, and engineering/R&D services across industries. Employs around 340,000 people in 50+ countries and provides end-to-end solutions from strategy and design to engineering.

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Date Posted: 2026-07-21