ASIC Verification Engineer
CapgeminiJob Title
ASIC Verification Engineer
Role Summary
Individual contributor responsible for verification of ARM-related IP blocks (examples: Cortex-A v9 CPU, Mali GPU, CSS600/CoreSight debug). Own verification activities across the project lifecycle including specification review, verification planning, test development, UVM environments, coverage analysis, debugging and gate-level simulation. This is a 100% remote role within the global verification team.
Experience Level
Mid-level. Proven 5+ years of hands-on ASIC verification experience is required.
Responsibilities
Primary responsibilities include ownership of verification for core IP blocks and collaboration with design and verification teams to improve quality and processes.
- Develop and execute verification plans and test cases for ARM-related IP (CPU, GPU, debug blocks).
- Design and maintain UVM/SystemVerilog testbenches and verification environments.
- Perform coverage collection and coverage analysis; track verification metrics.
- Perform formal verification, constrained-random testing, assertions, and gate-level simulation as required.
- Debug RTL and system-level failures; work with design teams to resolve issues.
- Reuse and adapt manufacturer-provided test benches and create C-based test cases to configure/test IP.
- Collaborate with the global verification team to refine processes and verification methodologies.
Requirements
Must-have technical skills and experience to perform the role.
- 5+ years of hands-on ASIC verification experience with modern methodologies (UVM/SystemVerilog).
- Experience with formal verification, constrained-random verification, assertions, and coverage-driven verification.
- Experience with gate-level simulation and verification metrics/KPIs.
- Strong understanding and practical experience with ARM-related IP: Cortex-A v9 CPU, Mali GPU, CSS600/CoreSight debug blocks.
- Hands-on experience writing C-based tests to configure and exercise ARM IP and reusing vendor test benches.
Nice-to-have
- Experience creating UVM-based environments for block and subsystem-level verification.
- Ability to read and understand RTL (SystemVerilog, Verilog, VHDL).
- Familiarity with revision control systems and CI/CD techniques for verification flows.
- Strong written/verbal communication, documentation, and cross-team collaboration skills.
Education Requirements
Not specified.
About the Company
Company: Capgemini
Headquarters: Paris, France
Global consulting, technology and engineering services firm offering digital and business transformation, cloud, AI, and engineering/R&D services across industries. Employs around 340,000 people in 50+ countries and provides end-to-end solutions from strategy and design to engineering.
