ASIC Verification Engineer
Design and execute verification for ASIC/VLSI components and subsystems as part of HPE's hardware engineering team. The role focuses on verification planning, developing SystemVerilog/UVM testbenches, simulation and debug, and coordinating with RTL designers, architects, firmware and validation teams.
Position is hybrid with an expectation of about two days per week in an HPE office (Durham, NC).
Mid-level β typically requires 3+ years of VLSI/ASIC verification experience.
Key responsibilities include planning and executing verification activities and communicating results to stakeholders.
Must-have skills and experience.
Nice-to-have: coverage-driven verification, formal methods, emulation/FPGA bring-up, and experience with major EDA vendors and FPGA tools.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent; coursework in VLSI design or related topics. Equivalent practical experience is acceptable.
Company: Hewlett Packard Enterprise
Headquarters: Spring, TX, United States
Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.
