ASIC Verification Engineer

Job Title

ASIC Verification Engineer

Role Summary

Engineer responsible for verification of ASICs and FPGA-based systems used in high-reliability, security-focused applications. Work includes developing and executing verification plans, building testbenches, running regressions, debugging failures, and automating EDA flows and reporting.

Experience Level

Mid-level (1–5 years of relevant ASIC/FPGA verification experience).

Responsibilities

Core verification and automation responsibilities:

• Develop verification plans from design requirements and architecture documents.
• Build and maintain SystemVerilog/UVM testbenches and reusable verification components.
• Create directed and constrained-random tests to validate functionality and corner cases.
• Develop assertions, drivers, monitors, predictors, scoreboards, checkers, and coverage models.
• Execute simulations and regression suites; analyze failures and drive closure.
• Review waveforms, logs, and coverage to identify root causes and verify fixes.
• Collaborate with RTL design, integration, and system teams to resolve issues.
• Automate EDA tool flows, regressions, and reporting using scripting.
• Document verification results, defects, and test status for technical reviews.

Requirements

Required technical skills and conditions; preferred items listed separately.

• Must-have: 1–5 years of ASIC/FPGA verification experience; strong SystemVerilog skills; SystemVerilog Assertions (SVA) or other assertion-based verification; experience with functional and code coverage analysis; ability to debug using waveforms and simulation logs; scripting experience (Python, Tcl, Bash, or similar); familiarity with common digital interfaces (UART, SPI, I2C, MIPI, LVDS, DMA); experience with EDA tools from Siemens, Cadence, Synopsys or similar; understanding of ASIC design and verification flows; ability to obtain and maintain a DoD Secret clearance (US citizenship required).
• Nice-to-have: Universal Verification Methodology (UVM); active Secret Clearance; formal verification methods; logic equivalence checking (LEC); CDC/RDC analysis; hardware security verification experience; DFT/ATPG and production test concepts; Automated Test Equipment (ATE) workflows; STIL/WGL vector familiarity; LVS/DRC and ASIC signoff exposure; experience debugging simulated vs measured waveform discrepancies.

Education Requirements

Bachelor's or graduate degree in Computer Engineering or Electrical Engineering is listed in the source posting. (The posting indicates these degrees; equivalent practical experience is not specified.)

About the Company

Company: Amentum

Headquarters: Germantown, MD, United States

Amentum provides technical and engineering services, specializing in government and defense support including facility operations, program management, systems engineering, and mission-critical logistics for national security and infrastructure programs.