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ASIC Verification Engineer

Capgemini
July 30, 2026
Full-time
Remote
Worldwide
$76,200 - $187,740 USD yearly
Verification Jobs, Level - Mid-Career

Job Title

ASIC Verification Engineer

Role Summary

Capgemini Engineering is seeking an ASIC Verification Engineer to own verification of ARM-related IP blocks (CPU, GPU, debug) for complex SoC designs. This is a 100% remote individual-contributor role focused on verification planning, test development, coverage analysis and debugging.

Experience Level

Mid-level — typically requires 5+ years of hands-on ASIC verification experience.

Responsibilities

Primary responsibilities include owning verification activities for core IP blocks and improving verification quality and processes.

  • Develop and own verification for ARM IP blocks such as CPU (Cortex-A v9), GPU (Mali), and Debug (CSS600/CoreSight).
  • Create verification plans, develop test cases, and build UVM environments.
  • Perform coverage analysis, assertions, constrained-random testing, and gate-level simulations.
  • Design and execute C-based tests to configure and validate ARM IPs; reuse vendor test benches when appropriate.
  • Debug RTL and verification failures; collaborate with design teams to improve requirements and specifications.
  • Participate in specification and architectural reviews and support the full project lifecycle.
  • Collaborate with the global verification team to improve methodologies, tools, and processes.

Requirements

Must-have skills and experience required for the role, followed by desirable qualifications.

  • Must-have: 5+ years of hands-on ASIC verification experience using UVM/SystemVerilog.
  • Must-have: Practical experience with formal verification, constrained-random techniques, assertions, coverage metrics and analysis, and gate-level simulation.
  • Must-have: Strong familiarity with ARM-related IPs: Cortex-A v9, Mali GPU, CSS600/CoreSight debug blocks.
  • Must-have: Experience writing and running C-based tests for ARM IPs and integrating vendor test benches.
  • Nice-to-have: Experience creating UVM block-level environments and reusing them at subsystem level.
  • Nice-to-have: Ability to read RTL (SystemVerilog/Verilog/VHDL), experience with revision control and CI/CD.
  • Nice-to-have: Strong documentation, process development, and cross-team collaboration skills.

Education Requirements

Not specified.


About the Company

Company: Capgemini

Headquarters: Paris, France

Global consulting, technology and engineering services firm offering digital and business transformation, cloud, AI, and engineering/R&D services across industries. Employs around 340,000 people in 50+ countries and provides end-to-end solutions from strategy and design to engineering.

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Date Posted: 2026-07-30