ASIC Verification Engineer

Job Title

ASIC Verification Engineer

Role Summary

Join E-Space's engineering team to design, simulate, and verify high-performance digital ASICs for satellite, IoT, and 5G communications. The role focuses on RTL and verification work across IP blocks, subsystems, and full-chip SoCs, collaborating with architects, RTL designers, and system teams.

Experience Level

Mid-level — typically requires around 5–10 years of ASIC verification experience.

Responsibilities

Primary responsibilities include developing and executing verification plans, building verification environments, and closing coverage gaps.

• Verify complex digital designs at IP, subsystem, and full-chip SoC levels.
• Translate architecture and micro-architecture specifications into executable verification plans.
• Design, develop, and maintain scalable UVM-based verification environments.
• Create high-quality testbenches in SystemVerilog; support VHDL and mixed-language environments.
• Drive functional and code coverage; analyze results and close coverage gaps.
• Debug issues using simulation, waveform analysis, assertions, and root-cause techniques.
• Collaborate with architects, RTL designers, and systems engineers to resolve issues.
• Document verification plans, methodologies, and results; report status to leadership.

Requirements

Must-have technical skills and experience for immediate productivity; nice-to-have items follow.

• Must-have: 5–10 years of ASIC verification experience for complex digital systems.
• Must-have: Strong SystemVerilog expertise and experience with UVM-based methodologies.
• Must-have: Working knowledge of VHDL and mixed-language verification environments.
• Must-have: Solid understanding of digital design fundamentals and experience verifying industry-standard protocols.
• Must-have: Strong debugging skills with simulation tools and waveform analysis; effective cross-functional communication.
• Nice-to-have: Advanced assertion-based verification or formal methods experience.
• Nice-to-have: Exposure to gate-level simulation, formal verification, emulation, or FPGA prototyping.
• Nice-to-have: Experience scaling verification infrastructure for large or multi-project SoCs and verifying SoCs integrating CPUs, DSPs, or mixed-signal blocks.

Education Requirements

Not specified.

About the Company

Company: E-Space

Headquarters: Saratoga, CA, United States

E-Space develops low Earth orbit (LEO) satellite systems to enable hyper-scaled Internet of Things (IoT) connectivity. The company designs advanced satellite hardware and communication systems to reduce costs, improve scalability, and deliver actionable intelligence from space.