ASIC Verification Engineer
CapgeminiJob Title
ASIC Verification Engineer
Role Summary
Capgemini Engineering seeks an individual contributor to own and execute ASIC verification for ARM-related IP blocks. The role focuses on verification planning, test development, coverage analysis, debugging, and improving verification methodologies across a global verification team.
This position is 100% remote.
Experience Level
Mid-level (5+ years of hands-on verification experience recommended).
Responsibilities
Primary duties include verification ownership across the project lifecycle and collaboration with design teams to ensure high-quality IP delivery.
- Plan and execute verification for ARM-related IPs (CPU Cortex-A v9, GPU Mali, Debug CSS600/CoreSight).
- Develop verification plans, test cases, and UVM/SystemVerilog environments.
- Create and run C-based test cases to configure and validate ARM IPs; reuse vendor-provided test benches when applicable.
- Perform coverage analysis, constrained-random verification, assertions, and formal verification activities.
- Run and analyze gate-level simulations (GLS) and key performance indicator tests.
- Debug RTL and verification failures; provide root-cause analysis and remediation guidance.
- Collaborate with cross-functional teams to refine specifications and support design debugging.
- Contribute to process, methodology, and tool improvements for the verification organization.
Requirements
Required skills and experience to perform the role effectively.
- Proven 5+ years of hands-on experience with verification methodologies (UVM/SystemVerilog, constrained-random, assertions, coverage metrics).
- Experience with formal verification techniques and gate-level simulation.
- Strong working knowledge of ARM-related IPs: CPU (Cortex-A v9), GPU (Mali), Debug (CSS600, CoreSight).
- Experience developing C-based test cases for ARM IP configuration and testing; ability to reuse manufacturer test benches.
- Experience in coverage analysis, testbench development, and verification debugging (GLS troubleshooting).
Nice-to-have:
- Experience creating UVM-based environments for block-level verification and reusing them at subsystem level.
- Ability to read and understand RTL (SystemVerilog, Verilog, VHDL).
- Familiarity with revision control systems and CI/CD practices for verification flows.
- Strong communication, documentation, and cross-team collaboration skills.
Education Requirements
Not specified.
About the Company
Company: Capgemini
Headquarters: Paris, France
Global consulting, technology and engineering services firm offering digital and business transformation, cloud, AI, and engineering/R&D services across industries. Employs around 340,000 people in 50+ countries and provides end-to-end solutions from strategy and design to engineering.
