ASIC Timing Engineer

Job Title

ASIC Timing Engineer

Role Summary

Drive static timing analysis (STA) and timing closure for Etched's next-generation AI ASICs. Work across block, cluster, and full-chip scopes and coordinate with Physical Design, Clocks, DFT, and methodology teams to deliver timing-converged designs.

Experience Level

Mid-level — the posting requests BS +5 years or MS +2 years of relevant Timing/STA experience as guidance.

Responsibilities

Key responsibilities include hands-on timing analysis, cross-team coordination, and improving timing convergence flows.

• Perform STA and timing closure at block, cluster, and full-chip levels.
• Develop and manage timing constraints; implement ECOs to fix timing paths.
• Collaborate with Physical Design, Clocks, DFX/DFT, and other teams to align timing and power convergence strategies.
• Analyze crosstalk and noise impacts and incorporate mitigations into timing closure.
• Enhance timing convergence flows and automation with methodology teams.
• Contribute to DFT timing closure for test modes such as scan and BIST.
• Ensure timing closure of digital logic and macros in AMS designs and IPs.

Requirements

Core technical skills and practical experience required; listed as must-have and nice-to-have.

Must-have

• Hands-on experience with full-chip and sub-chip STA, including fishtail analysis, Lint, CDC, and RDC checks.
• Proven experience generating and managing timing constraints and driving timing convergence.
• Ability to analyze and fix timing paths using ECOs, with emphasis on crosstalk and noise analysis.
• Strong understanding of RTL-to-netlist flow and use of industry-standard STA tools.
• Familiarity with deep sub-micron process nodes and associated timing modeling/convergence issues.

Nice-to-have

• Domain-specific STA experience with GPUs, CPUs, DPUs/network processors, or large SoCs.
• Experience in methodology/flow development and automation to improve timing convergence.
• Background handling timing closure for DFT modes and AMS IPs.

Education Requirements

BS in Electrical or Computer Engineering with 5+ years of relevant experience, or MS in Electrical or Computer Engineering with 2+ years of relevant experience. The posting also allows equivalent practical experience in lieu of the stated degrees.

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.