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ASIC/SOC Silicon Physical Design Engineer

MatX
July 29, 2026
Full-time
Remote friendly (Mountain View, California, United States)
Worldwide
Physical Design Jobs, Level - Senior

Job Title

ASIC/SOC Silicon Physical Design Engineer

Role Summary

Join MatX's silicon team to develop high-performance, energy-efficient GenAI ASICs. The role focuses on physical implementation and sign-off of blocks, subsystems, and full-chip designs across leading-edge process nodes.

This position works within the Physical Design organization and partners with RTL design, DFT, and verification teams to meet performance, power, area, and tapeout milestones. Candidates must be authorized to work in the United States and be onsite in Mountain View Tuesdays–Thursdays (hybrid schedule).

Experience Level

Senior — minimum 8 years of industry experience in ASIC Physical Design.

Responsibilities

Deliver physical design and sign-off for blocks, subsystems, and full-chip flows; drive reviews and coordinate cross-team execution toward tapeout.

  • Develop and maintain physical design methodology from RTL to GDSII for block, subsystem, and full-chip flows.
  • Own physical implementation tasks: partitioning, floorplanning, synthesis, place & route, clocking, and related flows.
  • Lead sign-off activities: equivalency checks, extraction, timing closure, power estimation, EMIR, and physical verification.
  • Plan and drive intermediate and sign-off reviews; report progress against silicon milestones such as design freeze and tapeout.
  • Collaborate closely with Design, DFT, and Verification teams to structure and optimize designs for PPA and sign-off.

Requirements

Must-have technical skills and experience for immediate contribution. Nice-to-have items listed separately.

  • At least 8 years of hands-on ASIC physical design experience (construction and sign-off) for blocks, subsystems, or full-chip.
  • Proven expertise with physical design flows and sign-off tools/processes across RTL-to-GDSII flows.
  • Strong scripting/programming skills, e.g. Perl, Python, TCL.
  • Experience coordinating with Design, Verification, and DFT teams to meet PPA and manufacturability goals.
  • Good interpersonal and written/verbal communication skills; able to lead reviews and report milestone status.

Nice-to-have:

  • Experience working with third-party design services partners.

Education Requirements

Bachelor of Science in Electrical Engineering or equivalent degree or equivalent practical experience. Relevant technical backgrounds (electrical engineering, computer engineering, computer science, or related fields) are acceptable as indicated by the posting.


About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.

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Date Posted: 2026-07-22