ASIC/SOC Silicon Physical Design Engineer
Join MatX's silicon team to develop high-performance, energy-efficient GenAI ASICs. The role focuses on physical implementation and sign-off of blocks, subsystems, and full-chip designs across leading-edge process nodes.
This position works within the Physical Design organization and partners with RTL design, DFT, and verification teams to meet performance, power, area, and tapeout milestones. Candidates must be authorized to work in the United States and be onsite in Mountain View Tuesdays–Thursdays (hybrid schedule).
Senior — minimum 8 years of industry experience in ASIC Physical Design.
Deliver physical design and sign-off for blocks, subsystems, and full-chip flows; drive reviews and coordinate cross-team execution toward tapeout.
Must-have technical skills and experience for immediate contribution. Nice-to-have items listed separately.
Nice-to-have:
Bachelor of Science in Electrical Engineering or equivalent degree or equivalent practical experience. Relevant technical backgrounds (electrical engineering, computer engineering, computer science, or related fields) are acceptable as indicated by the posting.
Company: MatX
Headquarters: Mountain View, California, USA
MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.
