ASIC/SoC Design Verification Senior Staff Engineer

Job Title

ASIC/SoC Design Verification Senior Staff Engineer

Role Summary

Senior verification engineer responsible for executing RTL functional verification for IP, subsystem, and SoC projects. You will develop and maintain UVM-based verification environments, drive coverage closure, debug complex issues using industry tools, and work directly with customers and global Synopsys teams.

Position is based in Ho Chi Minh City and focuses on delivering production-quality verification that prevents silicon respins and accelerates customer schedules.

Experience Level

Senior — the role expects experienced engineers. The posting specifies at least 3+ years of hands-on ASIC/SoC design verification experience.

Responsibilities

Key responsibilities include full lifecycle verification, environment development, and customer-facing delivery.

• Execute RTL functional verification from planning through coverage closure and signoff for IP, subsystem, and SoC projects.
• Design, implement, and maintain UVM-based verification environments and reusable components.
• Define functional coverage models and write SystemVerilog Assertions to drive coverage-driven verification.
• Debug complex design and verification issues using VCS and Verdi; perform root-cause analysis and coordinate fixes with RTL teams.
• Collaborate with global engineering teams and interface with customer engineering teams to define scope and verification strategies.
• Mentor junior verification engineers and contribute to verification methodology improvements.

Requirements

Must-have technical skills and experience; items listed as nice-to-have where appropriate.

• Must-have: 3+ years of hands-on ASIC/SoC design verification experience and strong end-to-end verification flow knowledge.
• Must-have: Proficiency in Verilog/SystemVerilog and experience with UVM-based verification environments.
• Must-have: Experience writing SystemVerilog Assertions and developing functional coverage models.
• Must-have: Strong debugging and root-cause analysis skills using tools such as VCS and Verdi.
• Must-have: Scripting and automation with Python, Perl, or Shell.
• Must-have: Experience with AMBA protocols (AXI, AHB, APB) and verifying complex bus-based systems.
• Nice-to-have: Experience with high-speed interfaces/protocols such as USB, PCIe, UCIe, DDR, or Ethernet.
• Nice-to-have: Proven experience mentoring engineers and working directly with customers on verification deliverables.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.