ASIC/SoC Design Engineer

Role Summary

The Silicon Design team at AMD is seeking an experienced ASIC/SoC Design Engineer to manage the RTL design lifecycle for next-generation embedded products. This role involves not just design but ensuring that the projects transition smoothly from ideation to production silicon while addressing complex SoC integrations.

Experience Level

The ideal candidate should have significant experience as a senior design engineer within ASIC and SoC projects, with a minimum of 2 successful production tape-outs. Candidates should excel in Verilog RTL coding, timing closure techniques, and possess physical design awareness.

Responsibilities

• Develop detailed micro-architecture specifications and implement major IP blocks in Verilog RTL, meeting performance, power, and area targets.
• Oversee the full ASIC development lifecycle including specification, RTL coding, verification, timing analysis, and post-silicon validation.
• Maintain timing constraints, conduct static timing analysis, and collaborate with physical design for timing closure.
• Integrate ASIC blocks into full-chip SoC environments and ensure protocol compliance.
• Work with verification teams for functional coverage and implement DFT and DFD features.
• Collaborate on physical design aspects such as floor planning and power grid design.
• Automate processes through scripting to improve design quality and efficiency.
• Engage cross-functionally with teams including architecture and CAD to resolve technical challenges.

Requirements

Candidates must demonstrate experience in senior design roles with proficiency in Verilog, complete ASIC design flows, and the integration of complex IP blocks. Knowledge of industry standards such as AMBA and PCIe protocols is essential. Strong communication skills and the capability to work collaboratively in cross-functional teams are imperative.

Education Requirements

A Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required for this position.