ASIC/RTL Design Engineer for High-speed Interfaces
QualcommJob Title
ASIC/RTL Design Engineer for High-speed Interfaces
Role Summary
Design and implement micro-architecture and RTL for high-speed mixed-signal interface IPs (SerDes, DDR, die-to-die) for integration across Qualcomm products. Work on end-to-end ASIC flow and collaborate with system architects, analog, verification, and physical design teams to deliver validated IPs.
Experience Level
Senior - requires extensive hands-on experience; the role specifies 7+ years of RTL and ASIC design experience.
Responsibilities
Deliver digital architecture, RTL, and support integration and bring-up of high-speed interface IPs.
- Architect and define digital design for SerDes, DDR, and die-to-die interconnect IPs in coordination with system and analog teams.
- Develop micro-architecture and implement RTL for complex mixed-signal IP blocks.
- Apply DSP, computer architecture, and ASIC techniques to improve power, performance, and area (PPA).
- Use front-end ASIC tools for lint, CDC analysis, DFT, synthesis, formal verification, and static timing analysis.
- Design and analyze DFT logic, including ATPG for stuck-at and transition delay fault coverage.
- Create hardware specifications and comprehensive design documentation.
- Collaborate with DV teams to define test plans, verify designs, and resolve bugs.
- Support floorplanning, placement, and timing closure with physical design teams.
- Support SoC integration, pre-silicon simulation, and post-silicon bring-up and debug.
Requirements
Key technical must-haves and relevant experience. Degree requirements are summarized separately under Education Requirements.
- 7+ years of experience in RTL and ASIC design.
- 5+ years of hands-on micro-architecture and digital design experience for mixed-signal IPs such as SerDes (PCIe, USB, UFS, MIPI), DDR PHY, PLLs, DACs, ADCs, and sensors.
- Proficiency with front-end ASIC design and verification tools (examples: VCS, Fusion Compiler, PrimeTime, Power Compiler, DFT Compiler, Spyglass).
- Experience with CDC analysis, linting, synthesis, formal verification, and static timing analysis workflows.
- Experience designing DFT logic and using ATPG for SAF and TDF coverage.
- Ability to collaborate across architecture, analog, DV, and PD teams and to produce clear design documentation.
- Preferred: background in low-power digital design techniques, computer architecture, digital signal processing, and automation scripting (Python or Perl).
Education Requirements
Qualifications in Science or Engineering are expected. The posting specifies: Bachelor's degree in Science, Engineering, or related field (with 4+ years of relevant ASIC experience) OR Master's degree in Science, Engineering, or related field (with 3+ years) OR PhD in Science, Engineering, or related field (with 2+ years). The role explicitly calls for a Master’s degree in Electrical Engineering, Computer Engineering, or a related field; a Ph.D. in Electrical Engineering is listed as preferred for senior candidates.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
