ASIC RTL Design Engineer

Job Title

ASIC RTL Design Engineer

Role Summary

Join a digital hardware team responsible for developing RTL and supporting full silicon development for high-performance compute subsystems. The role covers micro-architecture, synthesizable SystemVerilog/Verilog RTL, power optimization, SoC integration, verification support, FPGA/emulation bring-up, and post-silicon debug.

This is a remote role with customer-facing responsibilities: presenting technical solutions, gathering requirements, and supporting proof-of-concept and production phases.

Experience Level

Mid-level. No explicit years-of-experience specified.

Responsibilities

Main responsibilities include translating architecture into PPA-efficient RTL, integrating blocks at SoC level, and supporting pre- and post-silicon activities.

• Design synthesizable SystemVerilog/Verilog for compute datapaths (systolic arrays, vector/tensor units), on-chip memory, DMA engines, and control logic.
• Translate architecture specs into RTL focused on power, performance, and area; drive timing closure and handoffs to synthesis, physical design, and verification teams.
• Investigate and implement microarchitectural power optimizations (clock gating, operand gating, power islands, voltage domains).
• Build and refine RTL-level power models and collaborate on power budgeting and correlation across pre- and post-silicon milestones.
• Define and integrate chip-wide power management strategies (DVFS, idle/sleep states, wake sequencing) and coordinate with firmware and system thermal policies.
• Integrate blocks at SoC/top level: manage clock/reset domains, bus fabrics (AXI/CHI/NOC), and DFT; apply low-power design methodology (lint, CDC/RDC, synthesis constraints).
• Partner with architects, physical design, verification, firmware, and compiler/runtime teams on hardware–software co-design and ML kernel mapping (GEMM, convolution, attention).
• Support FPGA/emulation bring-up and post-silicon debug; analyze waveforms, evaluate power/performance tradeoffs, and propose ECOs.

Requirements

Must-have technical skills and practical experience; degree requirements are listed in Education Requirements below and have been omitted here to avoid duplication.

• Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals.
• Proven experience taking a design through the full lifecycle on real hardware (FPGA, SoC, or ASIC).
• Strong RTL design skills in SystemVerilog/Verilog for high-performance datapaths and control logic.
• Experience with low-power design techniques and RTL-level power modeling.
• SoC integration experience: clock/reset domains, bus fabrics (AXI/CHI/NOC), and DFT.
• Familiarity with industry EDA flows and tools (examples: DC/Genus, PrimeTime, VCS/Xcelium, SpyGlass, Verdi).
• Scripting proficiency (Python, Tcl) for automation and debug.
• Customer-facing communication skills: presenting technical solutions and documenting requirements.

Education Requirements

BSc or MSc in Electronics, Radio Engineering, Computer Engineering, or a related technical field.

About the Company

Company: INFT Solutions

Provides engineering staffing and contract services for semiconductor and electronics companies, including design, verification, and test support such as DFT and ATPG expertise.