ASIC RTL Design Engineer

Job Title

ASIC RTL Design Engineer

Role Summary

Join a digital hardware team and contribute across the full silicon development lifecycle: micro-architecture, RTL development, functional verification, implementation, on-hardware bring-up, and design documentation. The role is customer-facing and requires cross-team collaboration with architects, verification, physical design, firmware, and compiler/runtime teams.

This is a remote, long-term contract position focused on high-performance compute subsystems and low-power RTL design.

Experience Level

Mid-level. The posting expects engineers with practical ASIC/FPGA/SoC design experience; explicit years of experience were not provided.

Responsibilities

Primary duties include RTL design, PPA and power optimization, integration, and hardware bring-up.

• Design synthesizable SystemVerilog/Verilog for compute subsystems (systolic arrays, vector/tensor datapaths, on-chip memory, DMA engines, control logic).
• Translate architecture specifications into PPA-efficient RTL; drive timing closure and hand off to synthesis, physical design, and verification teams.
• Investigate and implement power optimizations: clock gating, operand gating, power islands, voltage domains, and datapath activity reduction.
• Build and refine RTL-level power models; support power budgeting and correlation across pre- and post-silicon milestones.
• Define and integrate chip-wide power management strategies (DVFS, idle/sleep states, wake sequencing) and coordinate with firmware and thermal policies.
• Integrate blocks at SoC/top level (clock/reset domains, bus fabrics such as AXI/CHI/NOC, DFT) and apply low-power design methodology (lint, CDC/RDC, synthesis constraints).
• Collaborate on hardware–software co-design and ML kernel mapping (GEMM, convolution, attention) with architects, compilers, and runtime teams.
• Support FPGA/emulation bring-up and post-silicon debug; analyze waveforms, evaluate power/performance trade-offs, and propose ECOs.
• Maintain design documentation and present technical solutions to customers.

Requirements

Must-have technical skills and experience for this role.

• Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals.
• Proven experience taking a design through the full lifecycle on real hardware (FPGA, SoC, or ASIC).
• Proficiency in synthesizable SystemVerilog/Verilog.
• Experience with RTL-level power optimization and power-management strategies.
• Scripting proficiency (Python, Tcl) and familiarity with industry EDA flows (e.g., DC/Genus, PrimeTime, VCS/Xcelium, SpyGlass, Verdi).
• Experience with clock/reset domain crossing, bus protocols (AXI, CHI) and DFT practices.
• Strong debugging skills for FPGA/emulation and post-silicon scenarios.
• Customer-facing communication skills and ability to document technical requirements and solutions.

Education Requirements

BSc or MSc in Electronics, Radio Engineering, Computer Engineering, or a related field.

About the Company

Company: INFT Solutions

Provides engineering staffing and contract services for semiconductor and electronics companies, including design, verification, and test support such as DFT and ATPG expertise.