ASIC Physical Design Technical Lead

Job Title

ASIC Physical Design Technical Lead

Role Summary

Lead full-chip ASIC physical design activities including floorplanning, power grid planning, place-and-route, timing closure, and physical verification for advanced-node chips. Partner with system, package, RTL, DFT, EDA vendors, and foundries to deliver tapeouts optimized for performance, power, and die size.

Experience Level

Senior — expects substantial prior ASIC physical design experience; typically 8+ years in physical design roles.

Responsibilities

Primary responsibilities include leading fullchip physical implementation and improving design flows.

• Develop fullchip floorplans considering architecture, IP placement, package, and foundry guidelines.
• Perform hierarchical implementation: partitioning, pin assignment, clock planning, and bump planning.
• Implement RTL-to-GDSII flow: floorplan, power grid design, place-and-route, static timing analysis, power integrity, physical verification, and equivalence checks.
• Design and verify chip-level clocking (mesh and H-tree approaches) and low-power strategies.
• Collaborate with RTL, DFT, package, system teams, EDA vendors, and foundries to define and validate signoff methodologies.
• Analyze and improve tool flows and methodologies; implement automation and workflow enhancements.
• Incorporate post-silicon validation feedback to adjust signoff and validation flows.
• Use AI tools to improve productivity and support design automation.

Requirements

Must-have technical skills and experience; preferred items noted where relevant.

• Hands-on experience with fullchip activities and RTL-to-GDSII tapeouts at 7nm/5nm/3nm or below.
• Proficiency with EDA tools such as Innovus, Tempus/PrimeTime, RedHawk/Voltus, and Calibre/Pegasus.
• Strong experience in static timing analysis, defining timing constraints, corners, and timing closure techniques.
• Expertise in power integrity analysis and fullchip power grid planning.
• Experience with hierarchical design flows, physical design convergence, and partitioning.
• Practical knowledge of low-power design methodologies (UPF) and chip-level clocking methods (H-tree, mesh).
• Experience working with foundry and IP vendors to define and validate signoff methodologies.
• Proficiency in Python; experience leveraging AI tools for productivity is desirable.

Education Requirements

Bachelor's degree in Electrical Engineering with 8+ years of physical design experience; or Master’s in Electrical Engineering with 6+ years; or PhD in Electrical Engineering with 3+ years. Fields: Electrical Engineering or related technical disciplines. Equivalent practical experience is acceptable.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).