ASIC Physical Design Staff Engineer

Job Title

ASIC Physical Design Staff Engineer

Role Summary

Work on RTL-to-GDSII physical implementation for high-performance interface IPs, test chips, and subsystems at advanced process nodes. The role spans synthesis, floorplanning, placement, clock-tree synthesis, routing, timing signoff, EM/IR analysis, and physical verification using Synopsys toolflows.

The position partners with IP architects, verification, and product teams to deliver tape-ready designs and to develop reusable implementation flows and CAD methodology.

Experience Level

Senior — typically requires 5+ years of hands-on ASIC physical implementation experience from RTL to GDSII at advanced nodes.

Responsibilities

Deliver and own the full physical implementation flow and improve team methodology and automation.

• Own RTL-to-GDSII implementation for interface IPs, subsystems, and test chips.
• Drive synthesis, floorplanning, power planning, placement, CTS, and routing using Synopsys tools (Design Compiler, ICC2, Fusion Compiler).
• Perform static timing analysis, EM/IR signoff, and physical verification to meet timing, power, and reliability targets.
• Debug complex timing, power, and physical issues in multi-million-gate designs and make timely decisions under tape-out pressure.
• Interface with IP architects, verification, and product engineering to define constraints and deliverable formats.
• Develop and refine implementation flows and CAD methodologies to improve PPA, turnaround time, and predictability.
• Contribute to scripting and automation (Perl, Tcl, Python) to streamline flows and improve productivity.

Requirements

Must-have technical skills and experience for immediate contribution.

• Experience: 5+ years of hands-on ASIC physical implementation from RTL to GDSII at advanced process nodes.
• Toolchain: Deep working knowledge of Synopsys tools including Design Compiler, ICC2, Fusion Compiler, PrimeTime, Star-RCXT, ICV, and RedHawk.
• Signoff experience: Proven responsibility for timing closure, signoff, or physical verification on recent tape-outs.
• Scripting: Strong scripting skills in Perl, Tcl, and Python for flow automation and CAD methodology development.
• Technical foundations: Solid understanding of timing constraint development, clock tree synthesis, EM/IR analysis, and physical verification flows.
• Debugging: Ability to trace critical paths, diagnose constraint issues, and propose practical fixes under schedule pressure.
• Nice-to-have: experience with IP subsystem implementation or multi-die integration.

Education Requirements

B.Tech or M.Tech in Electronics, Electronics & Communication, VLSI Design, Microelectronics, or equivalent degree; or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.